Labs
Lab 1
Lab 1: Introduction to Verilog Simulation and Synthesis
Pre-Lab Assignment
None.
Code-Check Requirement
None.
Files
Lab Overview:
In this lab, you will design a library of basic logic gates including a 2-input AND gate, a 2-input OR gate, and an inverter (INV gate). Using these basic components, one can build any combinational logic circuit.
Lab Procedure and Demo:
- 2-input AND gate (20 points)
- Follow the Verilog simulation tutorial to design a 2-input AND gate. Test your design exhaustively simulating all possible combinations. (10 points)
- Follow the Verilog synthesis tutorial ('starting from step 13) to download your 2-input AND gate design to the Spartan-3E Starter board. Test your design exhaustively trying all possible combinations. (10 points)
- 2-input OR gate (5 points)
- Design a 2-input OR gate. Test your design exhaustively simulating all possible combinations.
- Download your 2-input OR gate onto the Spartan-3E Starter board. Test your design exhaustively trying all possible input combinations.
- INV gate (5 points)
- Design an inverter (INV gate). Test your design exhaustively simulating all possible combinations.