Design Challenges
Design Challenges
The design challenges will augment your homework assignments for Chapter 5 and will be due at the beginning of lecture on each posted date. A total of 10 design challenges will be assigned, but you will only need to complete 9 of those design challenges to receive full credit. All design challenges will be graded out of 3 points.
Solutions to the design challenges will be presented in lecture on the day each design challenge is due (or shortly thereafter). As such, NO LATE design challenges will be accepted, but you are welcome to submit them early.
Note: Many of the following design challenges were previously used as exam questions.
Design Challenge 1 – Due Monday, Oct. 29
Create a high-level state machine that describes a 4-bit Up-Counter. The circuit has inputs Enable and StartOver, and a 4-bit output Cnt. If Enable is 1, on every clock cycle the counter should count up repeatedly and roll over to zero when the counter reaches the maximum 4-bit value. If StartOver is 1, the counter should output zero and keep outputting a zero until StartOver is de-asserted (goes back to zero). The StartOver input has priority over the Enable input. If both inputs are 0, the counter should keep it's current Cnt value. Using the RTL design method, convert the high-level state machine to a datapath and controller.
Design Challenge 2 – Due Wednesday, Oct 31
Design a high-level state machine for a digital thermostat for an air conditioner. The digital thermostat has a single-bit input on, and 8-bit input dtemp indicating the user's desired temperature, an 8-bit input ctemp providing the current temperature, and a single-bit output ac_on controlling the air conditioner. When on = 1, if the current temperature, ctemp, has been greater than the desired temperature, dtemp, for more than 5 minutes the thermostat will turn on the air conditioner by setting ac_on to 1. The air conditioner should remain on until the current temperature is less than or equal to the desired temperature.
Design Challenge 3 – Due Wednesday, Oct 31
Assuming a 1 Hz clock input, design a high-level state machine for a programmable flashing LED display. The flashing light display has an 8-bit input ontime indicating the number of seconds the LED should be illuminated, an 8-bit input offtime indicating the number of seconds the LED should not be illuminated, a single-bit input enable, and a single output led to control the LED. If the enable input is 0, the LED will remain off (led = 0). Otherwise, the flashing LED display will alternate between illuminating the LED (led = 1) and not illuminating the LED (led = 0) according to the number of seconds provided by the ontime and offtime inputs.
Design Challenge 4 – Due Wednesday, Nov 07
Design a high-level state machine for an event timer. The event timer has a 1-bit input e that will be 1 for one clock cycle indicating when each distinct event occurs. The event time has two 8-bit outputs, et and ot. The et output will output the elapsed time in clock cycles between the last two events. The ot output will output the number of times the measured elapsed time between the last two events exceeded a user-defined threshold specified by an 8-bit input th. Ensure that your event timer design works correctly regardless of how fast events occur. Note: You do not need to convert the state diagram to a datapath and controller.
Design Challenge 5 – Due Wednesday, Nov 07
Using the RTL design method, create an RTL design that counts the number of entries within a 128x32 register file A that are both greater than a 32-bit input Low and less than a 32-bit input High, i.e. Low < A[i] < High, outputting the count on an 8-bit output InRange. Create a datapath for your design, clearly labeling all data inputs/outputs, control inputs/outputs, and bit widths. Note: You do not need to convert your high-level state machine to an FSM.
Design Challenge 6 – Due Wednesday, November 14
Create an FSM to interface with the datapath provided. The overall circuit should interface to a 128x8 register file and find the average value between a user defined start address (start_addr) and end address (end_addr), inclusive. This operation should be performed when a one-bit input start is set to 1, and continue until the operation is completed. To indicate the circuit is performing the desired calculation, when finding the average value the circuit should set a one-bit output busy to 1. A one-bit done should be asserted for one cycle when the calculation is complete.
Design Challenge 7 – Due Wednesday, November 14
Create a high-level state machine that subtracts each register of a 256x16 register file A from the corresponding registers of another 256x16 register file B, storing the result back into the register file B. The HLSM should only begin when a bit input comp is 1.
Design Challenge 8 – Due Friday, November 16
Convert the following C-like code to a high-level state machine. Be sure to clearly specify the inputs, outputs, and local registers of your high-level state machine.
Outputs: byte vga, bit done
AVERAGE:
while(1) {
while(wait);
done = 0;
vga=0;
smu=2500;
i=0;
while ( i < 200 ) {
smu = smu - A[i];
i = i + 1;
}
vga = smu * -1;
done = 1;
}
Design Challenge 9 – Due Friday, November 16
Convert the following C code, which calculates the number of times the value b is not found within an array A consisting of 512 8-bit values, into a high-level state machine.
Outputs: byte freq, bit done
NFREQ:
while(1) {
while(!go);
done = 0;
i = 512;
tr = 0;
while( i > 0 ) {
if( a[i-1] != b ) {
tr = tr + 1;
}
i = i - 1;
}
freq = tr;
done = 1;
}
Design Challenge 10 – Due Friday, November 16
Convert the following C code, which calculates the maximum difference between any two numbers within an array VALS consisting of 256 8-bit values, into a high-level state machine.
Outputs: int max_diff, bit busy
MAX_DIFF:
while(1) {
while(!go);
busy = 1;
i = 0;
max = VALS[0];
min = VALS[0];
while( i < 256 ) {
if( VALS[i] < min ) {
min = VALS[i];
}
if( VALS[i] > max ) {
max = VALS[i];
}
i = i + 1;
}
max_diff = max - min;
busy = 0;
}