ECE 274A

Lab 2: Combinational Logic Design - Binary to ASCII Decoder

Starts: Week 4 (Sept 10 – Sept 14)
Demo Due: Week 4 (Sept 17 – Sept 21)
Code Due: Friday, Sept 21, 11:59 PM
Points: 85

Pre-Lab Assignment

Read the following lab description and procedures. Create a truth table and corresponding Boolean equations implementing the desired functionality of the Binary-To-ASCII Decoder design. (10 points)

Code-Check Requirement

An initial implementation for all Verilog modules and testbenches required for this lab assignment must be shown to your TA at the beginning of your scheduled lab on the week the assignment is due. (5 points)

Files

• Top Module (Lab2_Decode_Top.v)
• Verilog Module for ASCII Displayer (Lab2_ASCII_Displayer.v)
• Verilog Module for the LCD Interface (Lab2_LCD_Interface.v)
• Skeleton Verilog Module for the Binary-To-ASCII Decoder (Lab2_Binary_To_ASCII_Decoder.v)

Lab Overview

In this lab, you will build a binary to ASCII decoder in order to display 16 different ASCII characters on the LCD of the Spartan-3E FPGA board using the four available slide switches. The following figure shows a top-level view of all the Verilog components necessary to implement the desired functionality. You will only be responsible for designing and implementing the Binary-to-ASCII Decoder. The other components have been provided for you.

Brief Introduction to ASCII

ASCII is popular character-encoding scheme utilized to represent text using 8-bit values. A complete overview of the ASCII table can be found at: http://www.ascii-code.com. For example, the character '0' is represented in ASCII using the binary number 00110000. For each of the characters that we would like to display in this lab, you will need to determine the corresponding ASCII representation.

Binary-To-ASCII Decoder Description

The Binary-to-ASCII Decoder has four 1-bit inputs – In3, In2, In1, and In0 – and eight 1-bit outputs – ASCII_Val7, ASCII_Val6, ASCII_Val5, ASCII_Val4, ASCII_Val3, ASCII_Val2, ASCII_Val1, and ASCII_Val0. Based on the input values, your decoder should output the correct binary value representation as specified by the following table. For example, if the input is 0000, then the outputs ASCII_Val7 through ASCII_Val0 should equal 0011 0000 in order to display the ASCII character '0'.

In order to download your decoder to the Spartan-3E FPGA board, you must map the inputs and outputs of your top-level design to specific components on the physical board. For this project we will map the input signals – In3, In2, In1, and In0 – to the slide switches and map the LCD outputs to the LCD component as shown above. Additionally, the Clk input will mapped to the 50 MHz oscillator integrated on the Spartan-3E FPGA board, and the Rst input will be mapped to one of the buttons. The .ucf file used to specify these mappings is shown below.

Lab Procedure

1. Implement the Binary-To-ASCII Decoder component expressing each output as a Boolean equation in Verilog. (20 points)
2. Using a testbench, simulate only your Binary-To-ASCII Decoder to exhaustively test all possible input combinations. (20 points)
3. Synthesize and download your Binary-To-ASCII Decoder to the Spartan-3E Starter board and test your design exhaustively by trying all possible input combinations. (20 points)