ECE 274A

Laboratory Sections

We are sharing the lab with ECE 369. Otherwise, it's open lab and you are free to use the computers. You are permitted to use the computers by yourself, but you will need a minimum of 2 people in the lab to checkout hardware.

Laboratory Safety

Please watch the following video: UA ECE Laboratory Safety Video

Teaching Assistants

Laboratory Assignments

Students may choose to work in a group of two, or may choose to work on an individual basis if there is sufficient room in the lab. Graduate students are required to work on an individual basis. You must choose your lab partner(s) during the first scheduled lab period and inform your TA of your selection. Your lab partner will remain the same for the duration of the semester. Please choose your lab partner wisely. Please note that you may need to work outside of the lab section to complete all of your assignments.

A laboratory lecture will be provided on the first scheduled day for each lab assignment to present the lab assignment and detail what is required for that assignment. Each lab assignment (except for Lab 1) will have a pre-lab due at the beginning of the first scheduled day and a code-check due on the assigned day. The point values for each pre-lab assignment and code-check will be specified within each lab assignment.

All Verilog files for each lab assignment must be submitted via D2L to designated dropbox. The Verilog code must be submitted by 11:59PM on the Friday of the week each lab assignment is due. Only one code submission is required per group. Be sure to include the name of all students within your groups in the comments at the top of each submitted file, a text file listing the effort contributed by each group member, and follow the style guidelines discussed in lecture and lab assignments. If you do not submit your code, you will lose 10% from your lab grade. If you code does not adhere the Verilog formatting and style guidelines, you will lose 5% from your lab grade.

Labs must be finished on-time within your own scheduled lab section. NO LATE labs be accepted. NO extensions will be made for any lab assignments.

Lab Policies & Procedures

Lab Practical

Each student will additionally complete two one-hour lab practical which will be done on an individual basis. The purpose of the lab practicals is to ensure all students have the basic skills to specify and test a straightforward design using Verilog and the Xilinx IDE. At the beginning of the testing period students will be provided with a short problem statement and have one hour to design, test, and submit their solution and the accompanying testbench in a d2l drop box. The problem statement will cover the materials from lecture and previous labs and are not meant to include anything “tricky”. The TAs will monitor the exams but will not answer any questions or help to debug the code. Students may bring any written materials to the exam, but may not use any external or electronic reference materials during the testing period.

Laboratory Schedule

* For Monday lab sections, Lab 5 will be due on Nov 19.