ECE 474A/574A

Testfiles

assignment3_testfiles.tgz

Announcements and Clarifications

Overview

In this assignment, you will design and implement a high-level synthesis tool capable of creating a synthesizable high-level state machine (HLSM) description in Verilog from a simple C-like sequential program.

Commandline Arguments

Your program must be capable of utilizing commandline arguments specifying the location of the technology library and netlist files along with an option flag ("-ns") indicating that no scheduling of the input C-like sequential program should be performed. The following provides an example of the acceptable commandline arguments:

Your program must ensure the user has correctly provided the required commandline options and display a usage statement if the provided arguments are incorrect.

Verilog Code Generation

If the "-ns" commandline option is specified, you program should create a one procedure high-level state machine description (HLSM) that executes each sequential statement defined within the C-like sequential program within one-cycle (i.e. one state within the high-level state machine) where:

• The generated Verilog module should be named 'HLSM with Clk, Rst, Start, and Done as the first set of inputs/outputs as shown here:

• The resulting high-level state machine should include an initial Wait state and a final Final state used for controlling the execution of the resulting hardware description.
• The Wait state will wait for the Start input to be 1 before proceeding to execute the synthesized statements from the C-like sequential program.
• After the HLSM has executed the synthesized statements from the C-like sequential program, the Final state will assert the Done output to 1 for one cycle before returning to the Wait state.
• All inputs and outputs should be included in the model declaration in the order specified within the C-like sequential program.
• All input, outputs, and internal registers declared within the C-like sequential program are assumed to be 32-bit vectors and should be declared reg variables/outputs in the Verilog description.
• A single State register should be declared as a reg vector using the fewest number of bits possible to implement the resulting HLSM.
• The HLSM description should consist of a single procedure sensitive only to posedge Clk.
• Upon a reset indicated by the Rst input, all outputs and internal registers should be set to 0 and the State register should be assigned to the Wait state.
• The generated Verilog code must be synthesizable using Xilinx ISE 11.4.

C-like Sequential Program

Your program must be capable of taking as an input a C-like sequential program consisting of sequential statements, where:

• All empty lines should be ignored
• All line beginning with "//" are considered comment and should be ignored
• The C-like sequential program can be assumed to be fully space/tab delimited, i.e. at least one space or tab should appear between each token that needs to be parsed, including semicolons.
• All inputs must be explicitly declared on a single line using the format:

• All outputs must be explicitly declared on a single line using the format:

• All internal registers must be explicitly declared on a single line using the format:

• The following is a list of C statements that must be supported by your high-level synthesis tool.

• All names for inputs, outputs, and registers must be unique.
• All names for inputs, outputs, and registers are case sensitive and can consists of any number of letters or digits

When parsing te C-like sequential program, your high-level synthesis tool must provide descriptive error messages indicating if the netlist file does not adhere the above specifications.

ECE474A Groups

ECE474A students are optionally allowed to work in groups of 2 for this assignment. If you choose to work as a group, you must email the instructor by no later than Friday, March 5 indicating who your partner will be for the assignment (only one member need send the email). In addition, the comments section at the top of each submitted file must include the names of both students within your group.

Distribution Files

hlsyn.tgz

The distribution files hlsyn.tgz for this assignment include a basic example of checking commandline arguments along with a simple framework for using CMake. The distribution files also include five C-like sequential programs that will be used to test and grade your assignment.

Given the provided TAR/GZIPPED archive, the following commands can be used to extract, compile, and execute the program:

Submission Requirements and Grading

• All programming assignments must be submitted via D2L as a single ZIP or TAR/GZIPPED archive.
• All programming assignments must be implemented with C or C++ using the CMake cross platform make tools.
• All programming assignments will be compiled and tested using the ECE department server ece3.
• All programming assignments will be compiled using the following commands:

• Programs that fail to compile or terminate in a segmentation fault will receive a score of 0. NO EXCEPTIONS.
• The instructor will NOT answer any questions regarding assignments (by email or in person) on the day the assignment is due.
• All programming assignments will be tested using the provided public test files along with several additional private test files.
• Only the standard C and C++ libraries including STL may be utilized within your assignment.