ECE 474A/574A

TR 8:00-9:15AM, ECE 107

Instructor

Roman Lysecky, rlysecky@ece.arizona.edu
Office: ECE 356F
Office Hours: TR 10:45AM-11:45AM, or by appointment

Textbooks:

No textbook is required. The class notes/slides are sourced from the following materials:

• Digital Design, Frank Vahid, John Wiley & Sons, ISBN 0470044373
• Verilog for Digital Design, Frank Vahid and Roman Lysecky, John Wiley & Sons, ISBN 9780470052624
• Logic Synthesis and Verification Algorithms, Gary D. Hachtel and Fabio Somenzi, Springer, ISBN 0387310045
• Logic Minimization Algorithms for VLSI Synthesis, Robert K. Brayton, Gary D. Hathtel, C. McMullen, and Alberto L. Sangiovanni-Vincentelli, Kluwer Academic Publishers, ISBN 0898381649
• Introduction to Algorithms, Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest, McGraw-Hill, 0070131430
• Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, ISBN 0070163332

Overview:

This course is an introduction to Computer-Aided Logic Design. This is a highly-active research area, enabling the design of more and more complex digital systems. In this course we will mainly focus on three areas - specification, optimization, and the use of software tools.

We will look at how to specify functionality at a variety of abstractions, use industry-standard tools to simulate these designs, and investigate some of the underlying optimization techniques utilized.

Topics include, but are not limited to the following

• Design and implementation of sequential circuits
• Register-Transfer Level (RTL) Design
• Optimization and Tradeoffs of combinational and sequential circuits
• Exact and Heuristic Minimization of Two-Level Circuits
• Binary Decision Diagrams (BDDs)

Students will be expected to implement a variety of Verilog and C/C++ projects throughout the semester.

Grading:

Grades will be assigned using a strict 10% scale: 90% and above corresponds to an A, 80% and above to a B, 70% and above to a C, 60% and above to a D, and less than 60% to an E.

The grading will be based on a weighted sum as follows:

All grades will be posted on D2L.

Policies:

Punctuality: Please arrive on-time to class.

Reading: Please be prepared. Read over the material being covered in lecture before coming to class.

Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.

Late Assignments: Late assignments will only be accepted in extraordinary circumstances, (e.g., medical emergency, court summons).

Regrades: All requests for regrades must be submitted in writing within one week of the distribution of graded material.