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Assignment 2 (50 Points) - Due T February 16, 11:59PM

Testfiles

assignment2_testfiles.tgz *updated February 26, 1:42pm

Announcements and Clarifications

Mar 02, 2010: Assignment 2 re-submissions for segmentation faults (ECE 474a/574a) or critical path calculation correction (ECE 574a only are due by email by Friday, March 05 at 11:59PM.

Extended Submission Time: The submission time for your assignment has been extended by one day to T February 16, 11:59PM.

Output Registers: An output is not required to be explicitly connected to a register, but rather can be implicitly assumed to be connected to register. This implies that if an output within the behavioral netlist is not explicitly connected to a register, your program should internal instantiate the required register.

Program Outputs: The only outputs from your program should be the critical path value, the generated Verilog file, or an error message. Any outputs used for debugging or testing should not appear in your submitted code.

Behavioral Netlist File Format: For the behavioral netlist file format, you can assume that INPUTS, OUTPUTS, WIRES, and REGS declarations will come before component instantiations (although these declarations may be in any order).

Commandline Arguments: The verilogfile commandline argument specified with the -v option is the name of the Verilog file that your program should generate.

REG Component Clock and Reset Inputs: As all REG components need a clock and reset input to function correctly, the structural Verilog description generated by your program must have a clock and reset input. Please consult the provided Verilog component library for naming conventions for these signals.

Overview

In this assignment you will be modifying and extending the functionality developed in Assignment 1 by utilizing a new behavioral netlist input file format and adding an option for generating a synthesizable Verilog description.

Commandline Arguments

Your program must be capable of utilizing commandline arguments specifying the location of the technology library and netlist files along with an option flag ("-cp" or "-v") indicating that either the critical path calculation or the Verilog code generation should be performed should be performed. The following provides an example of the acceptable commandline arguments:

synthesizer -cp techfile netlist
or
synthesizer -v techfile netlist verilogfile

Your program must ensure the user has correctly provided the required commandline options and display a usage statement if the provided arguments are incorrect.

Verilog Code Generation

If the "-v" commandline option is specified, you program should create a structural Verilog description within the file specified by the commandline argument verilogfile for the logic circuit specified by a behavioral netlist file. The structural description should consist of component instantiations for which a behavioral description of each component will be provided within the Verilog component library. All inputs, outputs, wires, and registers are assumed to be 32-bit vectors. You generated Verilog code must be synthesizable. All generated Verilog description will be synthesized using Xilinx ISE 11.4.

Verilog Component Library

A Verilog component library is provided within the distribution files synthesizer.tgz for this assignment that provides a behavioral description of all components defined within the technology file.

Critical Path Calculation

If the "-cp" commandline option is specified, your program must calculate the critical path for a logic circuit specified by a behavioral netlist file given a technology library file. The critical path can be defined as the longest register to register delay path. For this assignment, your program must be able to calculate the critical path from any input to any output.

Given the technology library file and behavioral netlist file provided on the commandline, your program must create a direct acyclic graph (DAG) representation of the specific netlist and calculate the critical path. Assuming the input files do not contain any errors, the critical path should be output as:

Critical Path : 5.124 ns

ECE 574A: For this assignment, your program must be able to calculate the critical path from any input or internal register to any output or internal register.

Technology File

The technology library file provides the specification for those components that are available to be utilized within the netlist, where:

  • All empty lines should be ignored
  • All line beginning with "//" are considered comment and should be ignored
  • The technology library file can be assumed to be fully space/tab delimited, i.e. at least one space or tab should appear between each token that needs to be parsed, including semicolons.
  • Component declarations are declared on a single line using the format:
COMPONENTNAME : NUMBEROFINPUTS DELAY
  • All technology library files must declare the following components:
REG
ADD32
SUB32
MUL32
COMPGT
COMPLT
COMPEQ
MUX2x1
SHR
SHL
  • Component names are case sensitive and can consists of any number of letters or digits
  • The number of inputs for a component must be at least 1
  • The delay for each component is specified in nanoseconds as a real number (floating point).

When parsing the technology library file, your program must provide descriptive error messages indicating if the technology library file does not adhere the above specifications.

Behavioral Netlist File

The netlist file provides an acyclic connection of components specified within the technology library file, where

  • All empty lines should be ignored
  • All line beginning with "//" are considered comment and should be ignored
  • The netlist file can be assumed to be fully space/tab delimited, i.e. at least one space or tab should appear between each token that needs to be parsed, including semicolons.
  • All inputs must be explicitly declared on a single line using the format:
INPUTS : INPUT1 INPUT2 INPUTN
  • All outputs must be explicitly declared on a single line using the format:
OUTPUTS : OUTPUT1 OUTPUT2 OUTPUTN
  • All wires (internal connections between components) must be explicitly declared on a single line using the format:
WIRES : WIRE1 WIRE2 WIREN
  • All outputs are implicitly assumed to be REG components.
  • ECE574A: All internal registers must be explicitly declared on a single line using the format:
REGS : REG1 REG2 REG3
  • Component instantiations are declared on a single line using the following formats for specific components. Note that the component name and semicolon are only meant to indicate the format for specific components defined within the technology library and will not appear within the behavioral netlist.
REG:    o = b
ADD32:  o = a + b
SUB32:  o = a - b
MUL32:  o = a * b
COMPGT: o = a > b
COMPLT: o = a < b
COMPEQ: o = a == b
MUX2x1: o = sel ? i1 : i0
SHR:    o = a >> sh
SHL:    o = a << sh
  • All names for components, inputs, outputs, wires, registers, and instances must be unique.
  • All names for inputs, outputs, wires, and instances are case sensitive and can consists of any number of letters or digits

When parsing a behavioral netlist file, your program must provide descriptive error messages indicating if the netlist file does not adhere the above specifications.

ECE474A Extra Credit (5 points)

ECE474A students may earn up to 5 points extra credit by completing the ECE574A requirements for this assignment.

Distribution Files

synthesizer.tgz

The distribution files synthesizer.tgz for this assignment include a basic example of checking commandline arguments along with a simple framework for using CMake. The distribution files also include a public technology file, five public behavioral netlist files, and the Verilog component library that will be used to test and grade your assignment. In addition, one private technology file and five private behavioral netlist files will be also be used to test and grade your assignment.

Given the provided TAR/GZIPPED archive, the following commands can be used to extract, compile, and execute the program:

tar xvzf synthesizer.tgz
cd synthesizer
mkdir build
cd build
cmake ..
make
./src/synthesizer

Submission Requirements and Grading

  • All programming assignments must be submitted via D2L as a single ZIP or TAR/GZIPPED archive.
  • All programming assignments must be implemented with C or C++ using the CMake cross platform make tools.
  • All programming assignments will be compiled and tested using the ECE department server ece3.
  • All programming assignments will be compiled using the following commands:
mkdir build
cd build
cmake ..
make
./src/synthesizer
  • Programs that fail to compile or terminate in a segmentation fault will receive a score of 0. NO EXCEPTIONS.
  • The instructor will NOT answer any questions regarding assignments (by email or in person) on the day the assignment is due.
  • All programming assignments will be tested using the provided public test files along with several additional private test files.
  • Only the standard C and C++ libraries including STL may be utilized within your assignment.