ECE 576 - Homework Assignment 3
Due Wednesday, March 21 via D2L
Announcements and Clarifications:
Analysis of Impact on Bus Contention
In this assignment, you will extend the approximate timed system developed in HW Assignment 2 to add additional bus master components to simulate increased activity over the systems bus, and analyze how this increased activity affects system performance. Specifically, you will add two additional bus masters, including the SAD component from HW Assignment 1 and a commandline configurable bus traffic generator.
SAD Component
The SAD will compute the sum of absolute differences between two blocks of data stores within the memory. This computation should be customizable using #define's for NUM_BLOCKS, BLOCK_SIZE, INPUT1_ADDR, and INPUT2_ADDR. For each block, the result of the SAD calculation should be stored in memory as well as printed to the console/display with the current simulation time.
The following pseudocode provides a overview of the intended SAD component's functionality that should be customizable using a set of #define's with the resulting SystemC implementation.
#define BLOCK_SIZE 64
#define INPUT1_ADDR 0
#define INPUT2_ADDR 16384
#define SAD_OUTPUT_ADDR 32768
int i, v;
unsigned int block;
unsigned int sad;
for (block=0; block<NUM_BLOCKS; block++)
{
sad = 0;
for (i=0; i<BLOCK_SIZE; i++)
{
v = MEM[INPUT1_ADDR+(block*BLOCK_SIZE)+i] -
MEM[INPUT2_ADDR+(block*BLOCK_SIZE)+i];
if( v < 0 ) v = -v;
sad += v;
}
MEM[SAD_OUTPUT_ADDR+block] = sad;
}
Assuming all individual operations, e.g. additions, multiplication, comparisons, etc., require a 10 ns delay, incorporate wati() statements within the SAD component to model the appropriate delays. Using C/C++ comments within the code itself, provide a detailed annotation of the approximate time delays utilized.
Bus Traffic Generator
Add a configurable bus master component that will periodically read a random number of words ranging from 32 to 64 with a uniform distribution from memory using a burst transaction. A commandline argument should be utilized to define the period in ns at which these bus requests will be generated.
Performance Impact of Increased Bus Contention
Using the configurable bus traffic generator, analyze the overall systems performance with increased bus activity. Submit a 2 page Word or PDF document in IEEE two column format providing an overview of your systems implementation and resulting analysis of the system performance.