Lectures

R Jan 15, 2009: Course Overview and Introduction


T Jan 20, 2009: Introduction, State Machine Basics (FSM, HLSM)
R Jan 22, 2009: State Machines (HLSM)


T Jan 27, 2009: Transaction Level Modeling

Papers: Gajski, D., F. Cai. Transaction Level Modeling (TLM): An Overview, CODES+ISSS, 2003. PDF
R Jan 97, 2009: SystemC and TLM: Introduction


T Feb 03, 2009: SystemC and TLM: Introduction
R Feb 05, 2009: SystemC and TLM: Bus Functional Modeling

Papers: R. Atitallah, S. Niar, S.Meftali, J. Dekeyser. An MPSoC Performance Estimation Framework Using Transaction Level Modeling. International Conference on Embedded and Real-Time Computing Systems and Applications, 2007 PDF


T Feb 10, 2009: SystemC and TLM: Bus Arbitration
R Feb 12, 2009: Quiz 1, StateCharts

Papers:Harel, D. Statecharts: A Visual formalism for Complex Systems, Sci. Comput. Programming 8, pp. 231-274, 1987. PDF


T Feb 17, 2009: StateCharts
R Feb 19, 2009: HW/SW Codesign, Introduction


T Feb 24, 2009: HW/SW Partitioning

Papers: W. Wolfe. A Decade of Hardware/Software Codesign. IEEE Computer, 2003. PDF
R Feb 26, 2009: HW/SW Partitioning, Interfacing, JPEG Overview PDF
T Mar 03, 2009: HW/SW Partitioning, Synthesis from C

Papers: S. Edwards. The Challenges of Hardware Synthesis from C-like Languages. Design Automation and Test in Europe (DATE), 2005. PDF
R Mar 05, 2009: HW/SW Partitioning, Synthesis from C

Papers: D. Galloway. The Transmogrifier C Hardware Descriptiopn Language and Compiler for FPGAs. IEEE Computer, April 2003. PDF
T Mar 10, 2009: Exam 1
R Mar 12, 2009: HW/SW Partitioning, Performance Estimation
T Mar 17, 2009: No Class, Spring Break
R Mar 19, 2009: No Class, Spring Break


T Mar 24, 2009: HW/SW Partitioning, Performance Estimation
R Mar 26, 2009: HW/SW Partitioning, Power Estimation

Papers: Tiwari, V., Malik, S., Wolfe, A. Power analysis of embedded software: a first step towards software power minimization. International Conference on Computer Aided Design, 1994. PDF


T Mar 31, 2009: Instruction-Level Power Estimation, Introduction to Real-Time Scheduling

Papers: Varmayz, A., E. Debesz, I. Kozintsevz, B, Jacoby. Instruction-Level Power Dissipation in the Intel XScale

Embedded Microprocessor. Annual Symposium on Electronic Imaging Science & Technology (SPIE), 2005. PDF

R Apr 02, 2009: Real-Time Scheduling


T Apr 07, 2009: Quiz 2, Real-time Scheduling
R Apr 09, 2009: Real-Time Scheduling, Response Time Analysis



Upcoming Lecture Schedule (Subject to Change)

T Apr 14, 2009: Synchronous Dataflow, Static Scheduling
R Apr 16, 2009: Profiling, Warp Processing

Papers: R. Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006. PDF


T Apr 21, 2009: Paper Presentations:

Paper 2 (Deming and Hanyu): Lars Bauer, Muhammad Shafique, and Jörg Henkel. Run-time Instruction Set Selection in a Transmutable Embedded Processor DAC 2008, June 8–13, 2008, Anaheim, California, USA. PDF

Paper 3 (Saravanakrishnan and TBA): M. Abdelhalim, S. Habib. Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme. IEEE Computer Society Annual Symposium on VLSI (ISVLIS), 2008. PDF

Paper 4 (Mohamed and Varun): S. L. Sheey, S. Parameswarany, N. Cheungz. Novel Architecture for Loop Acceleration : A Case Study, (CODES+ISSS), 2005. PDF

Paper 5 (Varad and Ashish): James Balfour, William J. Dally, Fellow, David Black-Schaffer, Vishal Parikh, JongSoo Park. An Energy-Efficient Processor Architecture for Embedded Systems. IEEE Computer Architecture Letters, Vol. 7, No. 1, 2008. PDF

Paper 6 (Vijay and Sadiq): G. Stitt, F. Vahid, S. Nemetebaksh. Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems. IEEE Transactions on Embedded Computer Systems, January 2004. PDF

Paper 7 (Mike and Jeff): Z. Guo, A. B. Buyukkurt and W. Najjar. Input Data Reuse In Compiling Window Operations Onto Reconfigurable Hardware. Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES), 2004. PDF

R Apr 23, 2009: Exam 2


T Apr 28, 2009: Paper Presentations:

Paper 1 (Stephanie and Jacob): J. Ceng, J. Castrillon, W. Sheng, H. Scharwächter, R. Leupers, G. Ascheid, H. Meyr, T. Isshiki, H. Kunieda. MAPS: An Integrated Framework for MPSoC Application Parallelization. Design Automation Conference (DAC), 2008. PDF

Paper 8 (Carlos and Jong Chul): Stitt, G., F. Vahid, New Decompilation Techniques for Binary-level Co-processor Generation. International Conference on Computer-Aided Design (ICCAD), 2005. PDF

Paper 9 (Lin and Xuanxing): Baker, M. A., Parameswaran, V., Chatha, K. S., and Li, B. 2008. Power reduction via macroblock prioritization for power aware H.264 video applications. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2008. PDF

Paper 10 (Ravi and Aarthi): Zoltan Herczeg1, Akos Kiss1, Daniel Schmidt, Norbert Wehn, Tibor Gyimothy, XEEMU: An Improved XScale Power Simulator. PDF

Paper 11 (Tariq and Ishtiaq): E. Anderson, W. Peck, J. Stevens, J. Agron, F. Baijot, S. Warn, and D. Andrews, Supporting High-Level Language Semantics Within Hardware Resident Threads, 17th International Conference on Field Programmable Logic and Applications, August 2007. pp. 98-103. PDF

R Apr 30, 2009: No Class, Work on your project!


T May 05, 2009: No Class, Work on your project!