Analysis of one step majority logic decoders constructed from faulty gates
S. K. Chilappagari, M. Ivkovic, and B. Vasić, "Analysis of one step majority logic decoders constructed from faulty gates," Proc. IEEE Int. Symp. on Inform. Theory, Jul.9 - 14 2006, pp. 469 - 473.
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@inproceedings{CIV_06_ISIT,
abstract = {In this paper we propose an analytical method to evaluate the performance of one step majority logic decoders constructed from faulty gates. We analyze the decoder under the assumption that the gates fail independently. We calculate the average bit error probability of such a decoder and apply the method to the special case of projective geometry codes. The method, however, applies to any regular low-density parity-check code of girth at least six but the calculations are much simpler for the projective geometry codes. We present results for the bit error rate performance of four codes from projective planes},
author = {Chilappagari, S. K. and Ivkovic, M. and Vasić, B.},
booktitle = {Proc. IEEE Int. Symp. on Inform. Theory},
month = {Jul.9--14},
pages = {469--473},
title = {{A}nalysis of one step majority logic decoders constructed from faulty gates},
address = {Seattle, WA, USA},
year = {2006},
}