Fault tolerant memories based on expander graphs
S. K. Chilappagari and B. Vasić, "Fault tolerant memories based on expander graphs," Proc. IEEE Inform. Theory Workshop, Sep. 2 - 6 2007, pp. 126 - 131.
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Citation
@inproceedings{CV_07_ITW,
abstract = {In this paper we consider memories built from components subject to transient faults. We propose a fault-tolerant memory architecture based on {LDPC} codes and show the existence of memories which can tolerate constant fraction of failures in all the components. Our proof relies on the expansion property of the underlying Tanner graph of the code. We illustrate our results with specific numerical examples.},
author = {Chilappagari, S. K. and Vasić, B. },
booktitle = {Proc. IEEE Inform. Theory Workshop},
pages = {126--131},
title = {{F}ault tolerant memories based on expander graphs},
month={Sep. 2--6},
year = {2007},
address={Tahoe City, CA, USA},
}