Analytical performance of one-step majority logic decoding of regular LDPC codes
R. Radhakrishnan, S. Sankaranarayanan, and B. Vasić, "Analytical performance of one-step majority logic decoding of regular LDPC codes," Proc. IEEE Int. Symp. on Inform. Theory, Jun.24 - 29 2007, pp. 231 - 235.
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@inproceedings{RSV_07_ISIT,
abstract = {In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.},
author = {Radhakrishnan, R. and Sankaranarayanan, S. and Vasić, B.},
booktitle = {Proc. IEEE Int. Symp. on Inform. Theory},
pages = {231--235},
title = {{A}nalytical performance of one-step majority logic decoding of regular {LDPC} codes},
year = {2007},
month={Jun.24--29},
address={Nice, France},
}