University of Arizona
Department of Electrical and Computer Engineering

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Class Schedule

This schedule is subject to change throughout the semester. Please check back regularly for updates.

Week (Mon.) Monday Wednesday Friday
1 January 11 Course Overview, Introduction to Digital Logic, Binary Numbers zyBook Reading 1.1, 1.2, 1.3, 1.4, 1.5, and 1.12 due 9:30am, In class: Transistor level gate design exercise
2 January 18 No class (MLK Day) zyBook Reading 1.6, 1.7, 1.9, 1.10, 1.11, 1.15 due 9:30am , In class: Minimization exercises zyBook Reading 1.14, 1.8, 1.13, 1.16, 2.1, 2.2 due 9:30am, In class: Canonical form, Combinational Logic Design Examples, K-Maps
3 January 25 zyBook reading 2.3, 2.4, 2.5, 2.6 due 9:30am, In class: nand-based design zyBook reading 2.7, 2.8 due 9:30am, In-class: mux, decoder, encoder design zyBook reading 7.1, 7.2, 7.3, 7.4 due 9:30am, In-class: mux, decoder, encoder design
4 February 1 zyBook reading 3.1, 3.2, 3.3 due 9:30am, In class: D-latch, D-FF zyBook reading 3.4, 3.5 due 9:30am, In class: FSM Exam 1 (Boolean Algebra, Combinational Logic)
5 February 8 zyBook reading 3.6 due 9:30am, In class: FSM zyBook reading 3.7, 3.8 due 9:30am, In class: FSM zyBook reading 7.5 due 9:30am, Verilog: Sequential Logic Design
6 February 15 zyBook reading 3.12, 3.13 due 9:30am, In class: FSMs Sequential Logic Design Process zyBook reading 4.1, 4.2, 4.3 due 9:30am, In class: Adders, Signed Binary, Subtractor
7 February 22 zyBook reading 4.4, 4.5, 6.3 due 9:30am, In class: Comparators and multipliers register design zyBook reading 4.6, 6.6 due 9:30am, In class: ALUs, Load Registers Exam 2 (Ch 3)
8 February 29 zyBook reading 6.5 due 9:30am, In class: Multifunction Registers zyBook reading 6.4 due 9:30am, In class: Register files Shifters, Counters, Timers
9 March 7 Shifters, Counters, Timers, and Register Files Shifters, Counters, Timers, and Register Files Introduction to RTL Design
10 March 14 Spring Break Spring Break Spring Break
11 March 21 RTL Design zyBook reading 5.1-5.3 due 9:30am RTL Design zyBook reading 5.4, 5.5 due 9:30am Exam 3 (Ch 4 and 6)
12 March 28 RTL Design RTL Design zyBook reading 5.6, 5.7 due 9:30am RTL Design zyBook reading 5.8, 5.9 due 9:30am
13 April 4 No class/RTL Design Practice RTL Design Examples RTL Design Examples
14 April 11 RTL Design Examples RTL Design Examples Exam 4 (Ch 5)
15 April 18 RTL Design Examples: Insertion Sort RTL Design Examples: Insertion Sort, BRAM Sequential Optimizations - zyBook reading 3.9 due 9:30am
16 April 25 Sequential Optimizations - State Encoding, Mealy/Moore zyBook reading 3.10, 3.11 due 9:30am Sequential Optimizations - State Encoding, Mealy/Moore Critical Path Delay
17 May 2 Datapath Component Tradeoffs - Carry-Lookahead Adders, Multipliers zyBook reading 6.1, 6.2 due 9:30am FPGA Overview Final Exam (10.30am - 12noon)

Tentative Lab Schedule

Week Description Start Week Due Week Weight
3 Lab 1 - Introduction to Simulation and Synthesis January 25 January 25 4%
4 Lab 2 - Combinational Logic Design February 1 February 1 8%
5 Lab Practical (Combinational Logic) February 8 February 8 6%
6 Lab 3 - FSM February 15 February 15 4%
7 Lab 3 - FSM February 22 February 22 6%
8 Lab Practical (FSM) February 29 February 29 8%
9 Lab 3 - FSM Completion March 7 March 7 12%
10 Spring Break March 14 March 14
11 Lab 4 - Datapath Components and RTL Design March 21 March 21 6%
12 Lab Practical (Datapath) March 28 March 28 6%
13 Lab 4 - RTL-Single Player April 4 April 4 10%
14 Lab 4 - RTL-Two Player April 11 April 11 12%
15 Lab 4 - RTL-Single Player with BRAM April 18 April 18 8%
16 Lab Practical (RTL) April 25 April 25 10%