// ------------------------------------------------------------ // 
// Bus protocol ports, do not add to or delete
// ------------------------------------------------------------ // 
input         Bus2IP_Clk;
input         Bus2IP_Reset;
input  [31:0] Bus2IP_Data;
output        IP2Bus_MstRd_Req;
output        IP2Bus_MstWr_Req;
output [31:0] IP2Bus_Mst_Addr;
output [11:0] IP2Bus_Mst_Length;
output        IP2Bus_Mst_Type;
input         Bus2IP_Mst_CmdAck;
input         Bus2IP_Mst_Cmd_Timeout;
input  [31:0] Bus2IP_MstRd_d;
input         Bus2IP_MstRd_eof_n;
input         Bus2IP_MstRd_src_rdy_n;
output        IP2Bus_MstRd_dst_rdy_n;
output        done;

// ------------------------------------------------------------ // 
// Reg variables for user logic slave model s/w accessible register example
// ------------------------------------------------------------ // 
reg [31:0] blk1_mem_address, blk2_mem_address;
reg        exec_flag;
reg [31:0] SAD;
reg [7:0]  blk1 [0:15];

// ------------------------------------------------------------ // 
// Function to compute absolute difference
// ------------------------------------------------------------ // 
function [7:0] ABSDIFF;
   input [7:0] A, B;
   begin
      if( A >= B ) ABSDIFF = A - B;
      else ABSDIFF = B - A;
   end
endfunction
  
// ------------------------------------------------------------ // 
// master co-processor functionality  
// ------------------------------------------------------------ // 
always @( posedge Bus2IP_Clk ) begin
   if ( Bus2IP_Reset == 1 ) begin
      IP2Bus_MstRd_Req <= 0;
      IP2Bus_Mst_Addr <= 0;
      IP2Bus_Mst_Type <= 0;
      IP2Bus_Mst_Length <= 0;
      IP2Bus_MstRd_dst_rdy_n <= 0;
      m_state <= S_Wait; 
      SAD <= 0;  
   end
   else begin
      IP2Bus_MstRd_Req <= 0;
      IP2Bus_Mst_Addr <= 0;
      IP2Bus_Mst_Type <= 0;
      IP2Bus_Mst_Length <= 0;
      IP2Bus_MstRd_dst_rdy_n <= 0; 
      done <= 0;
	  
      case(m_state)
         S_Wait: begin
            if( exec_flag == 1 ) m_state <= S_ReadBlk1Init;
            else m_state <= S_Wait;
         end
   
         S_ReadBlk1Init: begin	
            SAD <= 0; 
            index <= 0;
            IP2Bus_MstRd_Req  <= 1;
            IP2Bus_Mst_Addr   <= blk1_mem_address;
            IP2Bus_Mst_Type   <= 1;
            IP2Bus_Mst_Length <= 16; // 16 bytes = 4 words
            IP2Bus_MstRd_dst_rdy_n <= 0;			
            if( Bus2IP_Mst_Cmd_Timeout ) m_state <= S_TimeOut;
            else if( Bus2IP_Mst_CmdAck ) m_state <= S_ReadBlk1;		      
            else m_state <= S_ReadBlk1Init;
         end
   
         S_ReadBlk1: begin   
            IP2Bus_MstRd_dst_rdy_n <= 0;					
            if( Bus2IP_MstRd_src_rdy_n==0 ) begin
               blk1[index+0] = Bus2IP_MstRd_d[7:0];
               blk1[index+1] = Bus2IP_MstRd_d[15:8];
               blk1[index+2] = Bus2IP_MstRd_d[23:16];
               blk1[index+3] = Bus2IP_MstRd_d[31:24];
               index <= index + 1;
            end			
            if( Bus2IP_MstRd_eof_n==0 ) m_state <= S_ReadBlk2Init;					
            else m_state <= S_ReadBlk1;
         end		
   
         S_ReadBlk2Init: begin
            index <= 0;
            IP2Bus_MstRd_Req  <= 1;
            IP2Bus_Mst_Addr   <= blk2_mem_address;
            IP2Bus_Mst_Type   <= 1;
            IP2Bus_Mst_Length <= 16; // 16 bytes = 4 words
            IP2Bus_MstRd_dst_rdy_n <= 0;			
            if( Bus2IP_Mst_Cmd_Timeout ) m_state <= S_TimeOut;
            else if( Bus2IP_Mst_CmdAck ) m_state <= S_Comp;		      
            else m_state <= S_ReadBlk2Init;
         end
         
         S_TimeOut: begin	
            m_state <= S_Wait;
         end
   
         S_Comp: begin   
            IP2Bus_MstRd_dst_rdy_n <= 0;					
            if( Bus2IP_MstRd_src_rdy_n==0 ) begin
               SAD <= SAD + ABSDIFF(Bus2IP_MstRd_d[7:0],   blk1[index+0]) + 
                            ABSDIFF(Bus2IP_MstRd_d[15:8],  blk1[index+1]) +
                            ABSDIFF(Bus2IP_MstRd_d[23:16], blk1[index+2]) +
                            ABSDIFF(Bus2IP_MstRd_d[31:24], blk1[index+3]);
               index <= index + 1;
            end			
            if( Bus2IP_MstRd_eof_n==0 ) begin
			   m_state <= S_Wait;	
			   done <= 1;
			end
            else m_state <= S_Comp;
         end	
      endcase
   end
end  
 
// ------------------------------------------------------------ // 
// memory-mapped register write interface
// ------------------------------------------------------------ // 
always @( posedge Bus2IP_Clk ) begin 
   if ( Bus2IP_Reset == 1 ) begin             
      exec_flag <= 0; 
      blk1_mem_address <= 0;
      blk2_mem_address <= 0;
   end
   else begin
      exec_flag <= 0;
      blk1_read_flag <= 0;
      case ( slv_reg_write_sel )
         8'b10000000 : begin
            blk1_mem_address <= Bus2IP_Data;  
         end    
   
         8'b01000000 : begin			
            exec_flag <= 1;
            blk2_mem_address <= Bus2IP_Data;   
         end    
      endcase  
   end
end

// ------------------------------------------------------------ // 
// memory-mapped register read interface
// ------------------------------------------------------------ // 
always @(slv_reg_read_sel) begin 
   case ( slv_reg_read_sel )
      8'b10000000 : slv_ip2bus_data <= blk1_mem_address;
      8'b01000000 : slv_ip2bus_data <= blk2_mem_address;
      8'b00100000 : slv_ip2bus_data <= SAD;
      default : slv_ip2bus_data <= 0;
   endcase
end