R Jan 13: Course Overview, Introduction, and Review
T Jan 18: Introduction and Review PDF, Finite State Machine (FSM) Specification PDF
R Jan 20: SystemC/TLM Introduction and Overview PDF
T Jan 25 SystemC and Transaction Level Modeling (TLM) PDF
*Guest Lecturer: Vijay Gopinath
R Jan 20: *Paper: Mu, J., R. Lysecky. Profile Assisted Online System-Level Performance and Power Estimation for Dynamic Reconfigurable Embedded Systems. Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.
*Guest Lecturer: Jingqing Mu
T Feb 01 SystemC and Transaction Level Modeling (TLM) PDF
R Feb 03 Transaction Level Modeling (TLM), Bus Functional/Arbitration Modeling
*
Paper: Gajski, D., F. Cai. Transaction Level Modeling (TLM): An Overview, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2003.
PDF
*
Paper: Atitallah, R., S. Niar, S. Meftali, J. Dekeyser. An MPSoC Performance Estimation Framework Using Transaction Level Modeling. International Conference on Embedded and Real-Time Computing Systems and Applications, 2007.
PDF
T Feb 08 Transaction Level Modeling (TLM), Bus Functional Modeling PDF
*
Datasheet: Xilinx PLB Master Burst Interface
PDF
R Feb 10 StateCharts PDF
*
Paper: Harel, D. Statecharts: A Visual formalism for Complex Systems, Sci. Comput. Programming 8, pp. 231-274, 1987.
PDF
T Feb 08 Transaction Level Modeling (TLM), Bus Functional Modeling (cont.) PDF, SystemC Simulation Semantics PDF
R Feb 17 Hardware/Software Codesign Introduction PDF
*
Paper: W. Wolfe. A Decade of Hardware/Software Codesign. IEEE Computer, 2003.
PDF
*
Article: M. Soni, J. Erickson. Case Study: High-level Synthesis - Ready for Prime-time? EE Times, Nov. 23, 2010
Link
T Feb 22 Hardware/Software Codesign Introduction PDF
*
Paper: W. Wolfe. A Decade of Hardware/Software Codesign. IEEE Computer, 2003.
PDF
*
Article: M. Soni, J. Erickson. Case Study: High-level Synthesis - Ready for Prime-time? EE Times, Nov. 23, 2010
Link
R Feb 24 Hardware/Software Partitioning: Communication Delays, MPEG Encoder Example UPDATED PDF
T Mar 01 Hardware/Software Partitioning: Communication Delays, MPEG Encoder Example UPDATED PDF
R Mar 03 Hardware/Software Partitioning: Power/Energy Estimation PDF
*
Paper: Tiwari, V., Malik, S., Wolfe, A. Power Analysis of Embedded Software: A First Step Towards Software Power Minimization. International Conference on Computer Aided Design, 1994.
PDF
T Mar 08 Review
R Mar 10 Exam 1
T Mar 15 No class. Spring Break.
R Mar 17 No class. Spring Break.
T Mar 22 Hardware/Software Partitioning: Power/Energy Estimation
R Mar 24 Hardware/Software Partitioning: Power Optimization (Voltage Scalable Processors)
*
Paper: Varmayz, A., E. Debesz, I. Kozintsevz, B, Jacoby. Instruction-Level Power Dissipation in the Intel XScale Embedded Microprocessor. Annual Symposium on Electronic Imaging Science & Technology (SPIE), 2005.
PDF
T Mar 29 High-Level Synthesis
*
Paper: D. Galloway. The Transmogrifier C Hardware Descriptiopn Language and Compiler for FPGAs. IEEE Computer, April 2003.
PDF
*
Paper: S. Edwards. The Challenges of Hardware Synthesis from C-like Languages. Design Automation and Test in Europe (DATE), 2005.
PDF
R Mar 31 High-Level Synthesis: Transmogrifier and Impulse CoDeveloper PDF
T Apr 05 Real-time Scheduling PDF
R Apr 07 Real-time Scheduling PDF
T Apr 12 Synchronous Dataflow, Static Scheduling PDF (note: these notes are rudimentary and need updating)
*
Article: Carbone, J. Back to the Basics: How to Measure Real-Time Performance.
Link
R Apr 14 Paper Presentations
*
Paper 0: K. Shankar, R. Lysecky. Non-Intrusive Dynamic Application Profiling for Multitasked Applications. Design Automation Conference (DAC), pp. 130-135, 2009.
PDF Presenters: Roman
T Apr 19 Paper Presentations
*Paper 1: Milakovich, A., V. Gopinath, R. Lysecky, J. Sprinkle. Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems. Workshop on Adaptive and Reconfigurable Embedded Systems (APRES), 2011.
Presenters: Roman
*
Paper 2: S. L. Sheey, S. Parameswarany, N. Cheungz. Novel Architecture for Loop Acceleration : A Case Study, (CODES+ISSS), 2005.
PDF Presenters: Pavan and Vihang
*
Paper 3: Z. Guo, A. B. Buyukkurt and W. Najjar. Input Data Reuse In Compiling Window Operations Onto Reconfigurable Hardware. Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES), 2004.
PDF Presenters: Maribel and Hussain
R Apr 21 Paper Presentations
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Paper 4: Baker, M. A., Parameswaran, V., Chatha, K. S., and Li, B. 2008. Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2008.
PDF Presenters: Adrian & George
*
Paper 5: Agron, J., D. Andrews, Building Heterogeneous Reconfigurable Systems With a Hardware Microkernel. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2009.
PDF Presenters: Tim & David
*
Paper 6: J. Aldis. Using SystemC to Build a System=on-Chip Platform. Embedded System Design, Jan/Feb 2011, pp. 14-27.
Link Presenters: Xiao & Lu
T Apr 26 Exam 2
R Apr 28 No Class
T May 03 No Class