Roman Lysecky (rlysecky@ece.arizona.edu)
Office Hours: T 10:45-11:45AM (or by appointment)
Office: ECE 356F
TR 9:30-10:45AM, ECE 107
Note: No textbook is required for this course. However, the folloiwng text is a good general textbook that may be useful for some aspects of this course.
High-Performance Embedded Computing, Wayne Wolf, Morgan Kaufman
Wayne Wolf's Book Website
The objective of this course is to provide students with the methods and techniques for supporting engineering design of complex, computer based systems. A design framework covering all levels of design from system-level modeling and simulation to design space exploration and design synthesis to dynamic optimizations will be discussed and applied in term projects. This course focuses on the engineering of systems that are comprised of heterogeneous, distributed, software, hardware, communication, and other components. The Spring 2008 course will focus on rapidly emerging embedded, heterogeneous, real-time systems with special emphasis on transaction level modeling and SystemC.
Most projects will focus on applying the methodologies, techniques, and concepts discussed in class to create and refine a system level model of a multimedia application using SystemC and transaction level modeling approaches. Students will work in small groups and select a project in conjunction with the instructor. Past projects have included JPEG image compression/decompression, distributed traffic control modeling, smart cruise controllers, networked embedded systems, intelligent appliance controllers, avionics applications, etc.
Project Description and Reported Template PDF,Word
Grading for the class will be performed on an individual basis. You will not
be competing with the other students for your grade. If all students do well
in the class, it is possible everyone will get an A. Your grade is only
dependent on the effort you put into the class. Letter grades will be
assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B,
70% and above to a C, 60% and above to a D, and less than 60% to an E.
The grading will be based on a weighted sum as follows:
40% | Midterms (2) | |
40% | Project | |
10% | Homework Assignments | |
10% | Quizzes (2-3) |
Punctuality: Please arrive on-time to class.
Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.
Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.
Regrades: All requests for regrades must be submitted in writing within one week of the distribution of graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem. Other problems within the same assignment might also be regraded, but such regrades will not negatively impact your score, i.e., regrades for problems not specifically requested will NOT result in a lower score.
Cell Phones: Please turn your cell phone off before you come to class.
Late Homework: Late homework assignments will be accepted for a maximum of two days after the due date. For each day your assignment is late, 10% of the total possible points will be deducted from your score.
Date | Publications | Presenter |
---|---|---|
Jan. 24 | Lysecky, R., G. Stitt, F. Vahid. Warp Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006. | N/A |
Feb. 07 | Narayan, S., F. Vahid, D. Gajski. System specification with the SpecCharts Language, IEEE Design & Test of Computers, Vol. 9, No. 4, Dec. 1992, pp. 6-13 | N/A |
Feb. 12 | Harel, D. Statecharts: A Visual formalism for Complex Systems, Sci. Comput. Programming 8 (1987), 231-274. | N/A |
Feb. 21 | Gajski, D., F. Cai. Transaction Level Modeling: An Overview, CODES+ISSS, 2003. | N/A |
Apr. 10 | R. Atitallah, S. Niar, S.Meftali, J. Dekeyser. An MPSoC Performance Estimation Framework Using Transaction Level Modeling. International Conference on Embedded and Real-Time Computing Systems and Applications, 2007.
S. Edwards. The Challenges of Hardware Synthesis from C-like Languages. Design Automation and Test in Europe (DATE), 2005. | Victor N/A |
Apr. 15 | G. Stitt, F. Vahid, S. Nemetebaksh. Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems. IEEE Transactions on Embedded Computer Systems, January 2004. | Sachi |
Apr. 17 | D. Galloway. The Transmogrifier C Hardware Descriptiopn Language and Compiler for FPGAs. IEEE Computer, April 2003.
K. Keutzer, S. Malik, A.R. Newton. From ASIC to ASIP: The Next Design Discontinuity. IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 84-90, 2002. | Jingqing Yaser |
Apr. 22 | Tensilica. Xtensa Architecture and Performance. Tensilica White Paper, 2005. | Adarsha & Anya |
Apr. 24 | J. Hanson. H.264 video encoding with Stretch's S5000 software-configurable processor. Video/Imaging DesignLine, 2005.
Z. Guo, A. B. Buyukkurt and W. Najjar. Input Data Reuse In Compiling Window Operations Onto Reconfigurable Hardware. Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES), 2004. | Arjun Zhen |
Apr. 29 | A. Gordon-Ross and F. Vahid. Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware. IEEE Transactions on Computers, 2005.
W. Klingauf. Systematic Transaction Level Modeling of Embedded Systems with SystemC. Design, Automation and Test in Europe (DATE), 2005. | Ram Karthik |
May 01 | L. Saldanha, R. Lysecky. Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits. | Lakshmi |
SUBJECT TO CHANGE
R | Jan 17: | Course Overview and Introduction | |
T | Jan 22: | Course Overview and Introduction (cont.) | |
R | Jan 24: | Warp Processing | |
T | Jan 29: | Finite State Machines (FSMs) | |
R | Jan 31: | FSMs, High-Level State Machines, Mealy vs. Moore | |
T | Feb 05: | Hierarchical and Concurrent FSMs | |
R | Feb 07: | SpecCharts | |
T | Feb 12: | StateCharts (cont.) | |
R | Feb 14: | Quiz 1, StateCharts (cont.) | |
T | Feb 19: | JPEG Image Compression/Decompression PDF | |
R | Feb 21: | Transaction Level Modeling, SystemC | |
T | Feb 26: | Transaction Level Modeling, SystemC | |
R | Feb 28: | Transaction Level Modeling, SystemC (cont.) | |
T | Mar 04: | Transaction Level Modeling, SystemC (cont.) | |
R | Mar 06: | Hardware/Software Partitioning, Interfacing (cont.) | |
T | Mar 11: | Hardware/Software Partitioning, Interfacing (cont.) | |
R | Mar 13: | Midterm 1, Hardware/Software Partitioning, Interfacing (cont.) | |
T | Mar 18: | No Class, Spring Break | |
R | Mar 20: | No Class, Spring Break | |
T | Mar 25: | Hardware/Software Partitioning, High-level Synthesis from C Lecture Notes | |
R | Mar 27: | Hardware/Software Partitioning, Profiling and Optimization | |
T | Apr 01: | Efficient Memory Structures | |
R | Apr 03: | Hardware/Software Partitioning, Performance Estimation | |
T | Apr 08: | Hardware/Software Partitioning, Performance Estimation | |
R | Apr 10: | Real-time Scheduling, Current/Future Research Topics | |
T | Apr 15: | Real-time Scheduling, Current/Future Research Topics | |
R | Apr 17: | Current/Future Research Topics | |
T | Apr 22: | Current/Future Research Topics | |
R | Apr 24: | Current/Future Research Topics | |
T | Apr 29: | Midterm 2 | |
R | May 01: | Quiz 2, Current/Future Research Topics | |
T | May 06: | TBD | |
R | May 07: | TBD |
Homework 1, Due Thursday, February 21 (beginning of lecture)
Homework 2, Due via email Friday, March 14, by 11:59PM
Sample Memory Initializaion File: mem.in
Homework 3, Due Tuesday, April 15 (beginning of lecture)