Roman Lysecky (rlysecky@ece.arizona.edu)
Office Hours: R 10:45-11:45AM
Office: ECE 320F
TR 9:30-10:45AM, ECE 107
The objective of this course is to provide students with methods and techniques for supporting engineering design of complex, computer based systems. A design framework covering all levels of design from system-level modeling and simulation to design space exploration and design synthesis to dynamic optimizations will be discussed and applied in term projects. This course focuses on the engineering of systems that are comprised heterogeneous, distributed, software, hardware, communication, and other components. The focus will be on rapidly emerging embedded, real-time systems and dynamic optimizations.
Designing a dynamic traffic control system intended to increase the efficiency of the flow of traffic through busy city streets while automatically adapting to traffic patterns and changing conditions, including weather, accidents, etc. While existing traffic control systems include some limited dynamic controls, such as ground induction loops and traffic cameras for monitoring the number of cars at a stop light, speed sensors embedded in the road, and synchronized light timing, such systems are often static in general. Throughout this semester, you will be designing and implementing a dynamic traffic control system that is scalable, distributed, and provides increased traffic flow and reduced wait times for drivers.
As the final project proposals have been very ambitious, please keep in mind the folloiwng priorites while implementing your final project. While achieving all proposed project goals is strongly desired, if time restrictions limit what your group is able to accomplish, please use the following priorities to guide what elements you should focus on in implementing the final project. NOTE: These are the main areas on which your final project will be graded.
Grading for the class will be performed on an individual basis. You will not
be competing with the other students for your grade. If all students do well
in the class, it is possible everyone will get an A. Your grade is only
dependent on the effort you put into the class. Letter grades will be
assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B,
70% and above to a C, 60% and above to a D, and less than 60% to an E.
The grading will be based on a weighted sum as follows:
| 25% | Final | |
| 20% | Midterm | |
| 40% | Project | |
| 10% | Homework Assignments | |
| 5% | Quizzes |
Punctuality: Please arrive on-time to class.
Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.
Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.
Regrades: All requests for regrades must be submitted in writing within one week of the distribution of graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem. Other problems within the same assignment might also be regraded, but such regrades will not negatively impact your score, i.e., regrades for problems not specifically requested will NOT result in a lower score.
Cell Phones: Please turn your cell phone off before you come to class.
Late Homework: Late homework assignments will be accepted for a maximum of two days after the due date. For each day your assignment is late, 10% of the total possible points will be deducted from your score.
Narayan, S., Vahid, F., Gajski, D.D.,
System specification with the SpecCharts Language,
IEEE Design & Test of Computers, Vol. 9, No. 4, Dec. 1992, pp. 6-13
Gajski, D.D., Vahid, F., Narayan, S., Gong, J.,
Specification and Design of Embedded Systems (Book Slides).
Harel, D.,
Statecharts: A Visual formalism for Complex Systems,
Sci. Comput. Programming 8 (1987), 231-274. Pages 231-250 Required
Knight, J., A Brief Overview of Statecharts, (PDF Slides), 2004.
Vahid, F., T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Chapter 8 Slides
Edwards, S., Dataflow Languages, (PDF Slides)
Santarini, M., Design Challenges Steer Automotive Electronics, EDN, January 05, 2006, PDF
Carbone, J. Back to the basics: How to Measure Real-time Performance, Embedded.com, 2005
*Newly Added* S. Brown, J. Rose
FPGA and CPLD Architectures: A Tutorial,
IEEE Design an Test of Computers, Vol. 13, No. 2, pp. 42-57, 1996
SUBJECT TO CHANGE
| R | Jan 12: | Course Overview and Introduction | |
| T | Jan 17: | Course Overview and Introduction | |
| R | Jan 19: | Finate State Machines (FSMs) | |
| T | Jan 24: | FSMs, High-Level State Machines, Mealy vs. Moore | |
| R | Jan 26: | Hierarchical and Concurrent FSMs, Statecharts | |
| T | Jan 31: | SpecCharts, Program State Machines | |
| R | Feb 02: | Synchronous Dataflow | |
| T | Feb 07: | JPEG Image Compression, PDF | |
| R | Feb 09: | Concurrent Processes | |
| T | Feb 14: | Concurrent Processes, FSM in C | |
| R | Feb 16: | Concurrent Processes, Threads, Real-time Systems | |
| T | Feb 21: | Real-time Scheduling, RTOS Performance | |
| R | Feb 23: | Behavioral Synthesis | |
| T | Feb 28: | Quiz 1, High-level/Algorithm Synthesis | |
| R | Mar 02: | High-level/Algorithm Synthesis | |
| T | Mar 07: | High-level Synthesis from C/C++ | |
| R | Mar 09: | High-level Synthesis from C/C++ | |
| T | Mar 14: | No Class, Spring Break | |
| R | Mar 16: | No Class, Spring Break | |
| T | Mar 21: | High-level Synthesis from C/C++, Midterm Review | |
| R | Mar 23: | Midterm | |
| T | Mar 28: | Hardware/Software Partitioning, Co-Processor Interfacing | |
| R | Mar 30: | Hardware/Software Partitioning, Co-Processor Interfacing | |
| T | Apr 04: | Profiling, Performance Analysis | |
| R | Apr 06: | Field Programmable Gate Arrays | |
| T | Apr 11: | Quiz 2, FPGAs | |
| R | Apr 13: | FPGAs | |
| T | Apr 18: | FPGAs (PDF), Profiling, Static and Dynamic (PDF) | |
| R | Apr 20: | Warp Processors PDF | |
| T | Apr 25: | Current/Future Research Topics | |
| R | Apr 27: | Current/Future Research Topics | |
| T | May 02: | Current/Future Research Topics | |
| T | May 09: | Final Exam, 8:00-10:00AM |
| Date | Publications | Presenter |
|---|---|---|
| T Feb 14: | Developing Applications Using Model-Driven Design Environments, K. Balasubramanian, A. Gokhale, G. Karsai, J. Sztipanovits, S. Neema. IEEE Computer, February 2006. |
Ajay Nair |
| T Feb 21: | Back to the basics: How to Measure Real-time Performance, J. Carbone Embedded.com, November 2005. |
N/A |
| R Feb 23: |
The Challenges of Hardware Synthesis from C-like Languages, S. Edwards Design Automation and Test in Europe (DATE), 2005. Corrected Link: Hardware Synthesis from C/C++ Models, G. De Micheli Design Automation and Test in Europe (DATE), 1999. Incorrect Link was to: Hardware Synthesis from C/C++, Abhijit Ghosh, Joachim Kunkel, Stan Liao Design Automation and Test in Europe (DATE), 1999. Just What is Algorithmic Synthesis?, B. Bowyer FPGA and Structured ASIC Journal, Decmber 2005. |
Aravind Oommen |
| T Feb 28: | The Softening of Hardware, F. Vahid. IEEE Computer, April 2003. |
Deepak Sreedharan |
| R Mar 02: | The Transmogrifier C Hardware Descriptiopn Language and Compiler for FPGAs, D. Galloway IEEE Computer, April 2003. |
N/A |
| R Mar 30: | A Decade of Hardware/Software Codesign, W. Wolfe IEEE Computer, April 2003. |
Lance Saldanha |
| T Apr 04: | From ASIC to ASIP: The Next Design Discontinuity, K. Keutzer, S. Malik, A.R. Newton IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 84-90, 2002. |
Don Cox |
| R Apr 06: | CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit, Z. A. Ye, A. Moshovos, S. Hauck, P. Banerjee International Symposium on Computer Architecture, pp. 225-235, 2000. |
Mark Hammerquist |
| T Apr 11: | Rapid SOC Development Using Automatically Generated Processors, Tensilica, Inc. XPRES White Paper |
Mario Riojas |
| R Apr 13: | New Decompilation Techniques for Binary-level Co-processor Generation , G. Stitt, F. Vahid International Conference on Computer-Aided Design (ICCAD), 2005. |
Vivek Nandakumar |
| T Apr 18: |
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors, J. Dean, J. Hicks, C. Waldspurger, W. Weihl, G Chrysos International Symposium on Microarchitecture (MICRO), 1997. |
Lahiru Ariyananda |
| R Apr 20: |
A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture, G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W.Bohm International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2001. Continuous profiling: where have all the cycles gone?, J. Anderson, L. Berc, J. Dean, S. Ghemawat, M. Henzinger, S. Leung, R. Sites, M. Vandevoorde, C. Waldspurger, W. Weihl ACM Transactiopns on Computer Systesm (TOCS), Vol. 15, No. 4, pp. 357-390, 1997. |
Dheepan Shanmugasundaram Audip Pandit |
| T Apr 25: |
The state-of-play in multi-processor and reconfigurable computing, C. Maxfield Programmable Logic DesignLine, 2006. H.264 video encoding with Stretch's S5000 software-configurable processor, J. Hanson Video/Imaging DesignLine, 2005. |
Sandeep Venishetti Rahul Kalra |
| R Apr 27: |
Optimality study of logic synthesis for LUT-based FPGAs, J. Cong, K. Minkovich International Symposium on Field Programmable Gate Arrays (FPGA), 2006. Power, Suddenly, We Care K. Morris FPGA and Programmable Logic Journal, April 26, 2005. |
Annapoorna Krishnaswamy Kartik Sihna |
Homework 1, Due Feb 14 (beginning of class)
Homework 2, Due Mar 07 (beginning of class)
Homework 3, Due Apr 04 (beginning of class)
Homework 4, Due Apr 27 (beginning of class)
