ECE 474A/574A

Testfiles

The following are example testfiles that will be utilized in grading Assignment 4: assignment4_testfiles.tgz.
Note: The test files utilized to grade the assignments may include additional testfiles and utilize only a subset of the provided testfiles.

Overview

In this assignment, you will design and implement a high-level synthesis tool capable of creating a synthesizable high-level state machine (HLSM) description in Verilog from a C-like sequential program supporting conditional and loop constructs while providing various scheduling alternatives.

Commandline Arguments

Your program must be capable of utilizing commandline arguments specifying the location of the technology library and netlist files along with several option flags indicating which scheduling algorithm should be utilized in synthesizing the C-like sequential program input. The following provides one example of the acceptable commandline arguments:

Usage Statement

Your program must ensure the user has correctly provided the required commandline options and display a usage statement if the provided arguments are incorrect.

Help Statement

Your program should provide a detailed description of all commandline options if the user provides the commandline options ("-help").

Verilog Code Generation

• The generated Verilog module should be named 'HLSM with Clk, Rst, Start, and Done as the first set of inputs/outputs as shown here:

• The resulting high-level state machine should include an initial Wait state and a final Final state used for controlling the execution of the resulting hardware description.
• The Wait state will wait for the Start input to be 1 before proceeding to execute the synthesized statements from the C-like sequential program.
• After the HLSM has executed the synthesized statements from the C-like sequential program, the Final state will assert the Done output to 1 for one cycle before returning to the Wait state.
• All inputs and outputs should be included in the model declaration in the order specified within the C-like sequential program.
• All input, outputs, and internal registers declared within the C-like sequential program are assumed to be 32-bit vectors.
• All outputs and internal registers should be declared as reg variables/outputs in the Verilog description.
• A single State register should be declared as a reg vector using the fewest number of bits possible to implement the resulting HLSM.
• The HLSM description should consist of a single procedure sensitive only to posedge Clk.
• Upon a reset indicated by the Rst input, all outputs and internal registers should be set to 0 and the State register should be assigned to the Wait state.
• The generated Verilog code must be synthesizable using Xilinx ISE 11.4.

Scheduling Algorithms

Your program must support two alternative scheduling algorithm. The no scheduling algorithm ("-ns") is required by all programs. In addition, you program must support one of the listed optional algorithms.

The scheduling algorithm will be utilized to schedule all C-like sequential statements, including those contained within conditional or loop statements, but will not be utilized to synthesize the conditional and loop statements themselves.

No Scheduling Algorithm ("-ns") Required

If the "-ns" commandline option is specified, you program should create a one procedure high-level state machine description (HLSM) that executes each sequential statement defined within the C-like sequential program within one-cycle (i.e. one state within the high-level state machine).

List_L ("-listl")

If the "-listl" commandline option is specified, you program should create a one procedure high-level state machine description (HLSM) such that all sequential statements, including those contained within each conditional or loop statement, are scheduled using the List_L scheduling algorithm, such that:

• Available resource types include, multiplier, adder/subtractor, and logic/logical.
• The multiplier resource only supports multiplication.
• The adder/subtractor resource supports addition and subtraction.
• The logic/logical resource type supports all other operations, including comparisons, shift, and ternary operators.
• All resources are assumed to have a 1 cycle delay.
• The user should be able to specify the resource constraints for each resource type using commandline options.

List_R ("-listr")

If the "-listr" commandline option is specified, you program should create a one procedure high-level state machine description (HLSM) such that all sequential statements, including those contained within each conditional or loop statement, are scheduled using the List_R scheduling algorithm, such that:

• Available resource types include, multiplier, adder/subtractor, and logic/logical.
• The multiplier resource only supports multiplication.
• The adder/subtractor resource supports addition and subtraction.
• The logic/logical resource type supports all other operations, including comparisons, shift, and ternary operators.
• All resources are assumed to have a 1 cycle delay.
• The user should be able to specify the latency constraint as a commandline option.

Extra Credit (12.5 points)

Extra credit may be awarded if all three scheduling alternatives are implemented.

Base C-like Sequential Program

Your program must be capable of taking as an input a C-like sequential program consisting of sequential statements, where:

• All empty lines should be ignored
• All line beginning with "//" are considered comment and should be ignored
• The C-like sequential program can be assumed to be fully space/tab delimited, i.e. at least one space or tab should appear between each token that needs to be parsed, including semicolons.
• All inputs must be explicitly declared on a single line using the format:

• All outputs must be explicitly declared on a single line using the format:

• All internal registers must be explicitly declared on a single line using the format:

• The following is a list of C statements that must be supported by your high-level synthesis tool.

• All names for inputs, outputs, and registers must be unique.
• All names for inputs, outputs, and registers are case sensitive and can consists of any number of letters or digits

When parsing the C-like sequential program, your high-level synthesis tool must provide descriptive error messages indicating if the netlist file does not adhere the above specifications.

Support for Conditional and Loop Structures

In additional to the base C-like sequential program, your program must provide support for at least two of the following conditional and loop constructs as described below.

if statement

The if statement will execute the sequential statements within the if statement if the conditional is true. The conditional is assumed to be true if the value is non-zero and false if the value if zero. The following provides the required format for the supported if statement:

while loop

The while loop will continue to execute as long as the conditional is true, where the conditional is checked at the beginning of each loop execution. The conditional is assumed to be true if the value is non-zero and false if the value if zero. The following provides the required format for the supported while loop:

do...while loop

The do...while loop will continue to execute as long as the the conditional is true, where the conditional is checked at the end of each loop execution. The conditional is assumed to be true if the value is non-zero and false if the value if zero. The following provides the required format for the supported do...while loop:

Extra Credit (12.5 points)

Extra credit may be awarded if all three conditional and loop statements are implemented.

ECE 474A Groups

ECE 474A students are optionally allowed to work in groups of 2 for this assignment. If you choose to work as a group, you must email the instructor by no later than Monday, November 1 indicating who your partner will be for the assignment (only one member need send the email). In addition, the comments section at the top of each submitted file must include the names of both students within your group.

README File

A README file must be included in your src directory and include the following information:

• Name (or names for ECE 474A students working in a group)
• List of scheduling algorithm supported by your program and details for how to specify any additional commandline arguments.
• List of the conditional and loop statements supported by your program.

Testfiles

You must submit at least five test inputs files utilized to test and verify correct execution of your scheduling algorithm for the supported conditional and loop statements.

Distribution Files

hlsyn.tgz

The distribution files hlsyn.tgz for this assignment include a basic example of checking commandline arguments along with a simple framework for using CMake. The distribution files also include five C-like sequential programs that will be used to test and grade your assignment.

Given the provided TAR/GZIPPED archive, the following commands can be used to extract, compile, and execute the program:

Submission Requirements and Grading

• All programming assignments must be submitted via D2L as a single ZIP or TAR/GZIPPED archive.
• All programming assignments must be implemented with C or C++ using the CMake cross platform make tools.
• All programming assignments will be compiled and tested using the ECE department server ece3.
• All programming assignments will be compiled using the following commands:

• Programs that fail to compile or terminate in a segmentation fault will receive a score of 0. NO EXCEPTIONS.
• No debugging outputs should appear in your submitted code.
• No libraries outside of the standard C and C++ libraries should be utilized within your assignment.
• The instructor will NOT answer any questions regarding assignments (by email or in person) on the day the assignment is due.
• All programming assignments will be tested using the provided public test files along with several additional private test files.