Lab 1: Introduction to Verilog Simulation and Synthesis

Starts: Week 3 (Jan 26-Jan 30)
Demo Due: Week 3 (Jan 26-Jan 30)
Code Due: Friday, Jan 30, 11:59PM
Points: 30

Pre-Lab Assignment

None.

Files

Lab Overview:

In this lab, you will design a library of basic logic gates including a 2-input AND gate, a 2-input OR gate, and an inverter (INV gate). Using these basic components, one can build any combinational logic circuit.

Lab Procedure and Demo:

  1. 2-input AND gate (20 points)
    • Follow the Verilog simulation tutorial to design a 2-input AND gate. Test your design exhaustively simulating all possible combinations. (10 points)
    • Follow the Verilog synthesis tutorial to download your 2-input AND gate design to the Spartan-3E Starter board. Test your design exhaustively trying all possible combinations. (10 points)
  2. 2-input OR gate (5 points)
    • Design a 2-input OR gate. Test your design exhaustively simulating all possible combinations.
    • Download your 2-input OR gate onto the Spartan-3E Starter board. Test your design exhaustively trying all possible input combinations.
  3. INV gate (5 points)
    • Design an inverter (INV gate). Test your design exhaustively simulating all possible combinations.

Lab Report/Code Requirements

No lab report is required for the first lab.


ECE 274

Labs

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