//--------------------------------------------------------------------
//
// Verilog Debugging Seminar Example
// Roman Lysecky
// Copyright (C) 2008, All Rights Reserved
// 
//--------------------------------------------------------------------

`timescale 1 ns/1 ns
module Testbench();
    
   reg Clk_s, Rst_s;
   reg Clr_s, X_s, Y_s;
   wire EqCnt_s;
   wire OvMax_s;
	
   ExFSM CompToTest(Clk_s, Rst_s, Clr_s, X_s, Y_s, EqCnt_s, OVMax_s);
   
   // Clock Procedure
   always begin
      Clk_s <= 0;
      #10;
      Clk_s <= 1;
      #10;
   end   // Note: Procedure repeats
   
   // Vector Procedure
   initial begin
      Rst_s <= 1;
      Clr_s <= 0;
      X_s <= 0;
      Y_s <= 0;
      @(posedge Clk_s);
      #5 if (EqCnt_s != 0 || OvMax_s != 0) $display("%t: Reset failed", $time);

      Rst_s <= 0;

      // (X == Y) Wait for two clocks cycles
      X_s <= 0;
      Y_s <= 0;
      @(posedge Clk_s);
      @(posedge Clk_s);
      if (EqCnt_s != 2 || OvMax_s != 0) $display("%t: Eq (XY=00) 2 Cycle Test failed", $time);
      
      // (X != Y) Wait for two clocks cycles
      X_s <= 1;
      Y_s <= 0;
      @(posedge Clk_s);
      #5 if (EqCnt_s != 2 || OvMax_s != 0) $display("%t: Neq (XY=10) Test failed", $time);

      // (X != Y) Wait for two clocks cycles
      X_s <= 0;
      Y_s <= 1;
      @(posedge Clk_s);
      #5 if (EqCnt_s != 2 || OvMax_s != 0) $display("%t: Neq (XY=01) Test failed", $time);

      // (X == Y) Wait for five more clocks cycles
      X_s <= 0;
      Y_s <= 0;
      @(posedge Clk_s);
      @(posedge Clk_s);
      @(posedge Clk_s);
      @(posedge Clk_s);
      @(posedge Clk_s);
      #5 if (EqCnt_s != 7 || OvMax_s != 0) $display("%t: Eq (XY=00) 7 Total Cycles Test failed", $time);

      // Test Max signal
      @(posedge Clk_s);
      #5 if (EqCnt_s != 7 || OvMax_s != 1) $display("%t: Max Test failed", $time);

      // Clear
      Clr_s <= 1;
      @(posedge Clk_s);
      #5 if (EqCnt_s != 0 || OvMax_s != 0) $display("%t: Max Clear failed", $time);

      // (X == Y) Wait for three clocks cycles
      Clr_s <= 0;
      X_s <= 1;
      Y_s <= 1;
      @(posedge Clk_s);
      @(posedge Clk_s);
      @(posedge Clk_s);
      #5 if (EqCnt_s != 3 || OvMax_s != 0) $display("%t: Eq (XY=11) 3 Cycle Test failed", $time);

      // Clear
      Clr_s <= 1;
      @(posedge Clk_s);
      #5 if (EqCnt_s != 0 || OvMax_s != 0) $display("%t: Clear from 3 test failed", $time);

   end
endmodule
//--//