//--------------------------------------------------------------------
//
// Verilog Debugging Seminar Example
// Roman Lysecky
// Copyright (C) 2008, All Rights Reserved
// 
//--------------------------------------------------------------------

`timescale 1ns / 1ns
module ExFSM(Clk, Rst, Clr, X, Y, EqCnt, OvMax);

   input Clk, Rst;
   input Clr, X, Y;
   output reg [2:0] EqCnt;
   output reg OvMax;
 
   parameter S_Neq = 'b000,
             S_Eq1 = 'b001,
             S_Eq2 = 'b010,
             S_Eq3 = 'b011,
             S_Eq4 = 'b100,
             S_Eq5 = 'b110,
             S_Eq6 = 'b110,
             S_Eq7 = 'b111,
             S_Max = 'b1000;
             
   reg [3:0] State, StateNext;
   
   // CombLogic
   always @(State, Clr, X) begin
      OvMax <= 0;
      EqCnt <= 3'b000;
      case (State) 
         S_Neq: begin
            EqCnt <= 0;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq1;
            else
               StateNext <= S_Neq;
         end

         S_Eq1: begin
            EqCnt <= 1;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq2;
            else
               StateNext <= S_Eq1;
         end

         S_Eq2: begin
            EqCnt <= 2;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq3;
            else
               StateNext <= S_Eq2;
         end

         S_Eq3: begin
            EqCnt <= 3;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq4;
            else
               StateNext <= S_Eq3;
         end

         S_Eq4: begin
            EqCnt <= 4;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq5;
            else
               StateNext <= S_Eq4;
         end

         S_Eq5: begin
            EqCnt <= 5;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq7;
            else
               StateNext <= S_Eq6;
         end

         S_Eq6: begin
            EqCnt <= 6;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Eq7;
            else
               StateNext <= S_Eq6;
         end

         S_Eq7: begin
            EqCnt <= 7;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else if ( (X == 1 && Y == 1) || 
                (X == 0 && Y == 0) )
               StateNext <= S_Max;
            else
               StateNext <= S_Eq7;
         end

         S_Max: begin
            OvMax <= 1;
            if(Clr == 1) 
               StateNext <= S_Neq;
            else 
               StateNext <= S_Max;
         end

         default: begin
            StateNext <= S_Neq;
         end
      endcase
   end

   // StateReg 
   always @(posedge Clk) begin
      if (Rst == 1 ) 
         State <= S_Neq;
      else
         State <= StateNext;
   end
	
endmodule