Roman Lysecky (email@example.com)
Office Hours: M 12:00-1:00PM, T 10:45-11:45AM, R 10:45-11:45, F 10:45-11:45, or by appointment.
Office: ECE 356F
MWF 12:00-12:50PM, ILC 140
|Section 2:||T 8:00AM-10:50AM,||ECE 301,||TA: Derek Nielson|
|Section 3:||T 2:00PM-4:50PM,||ECE 301,||TA: Lance Saldanha|
|Section 6:||R 11:00AM-1:50PM,||ECE 301,||TA: Derek Nielson|
|Section 8:||F 2:00PM-4:50PM,||ECE 301,||TA: Lance Saldanha|
Lance Saldanha, (firstname.lastname@example.org)
Office Hours: TBD
Derek Nielson, (email@example.com)
Office Hours: TBD
Digital Design, Frank Vahid, John Wiley and Sons
Frank Vahid's Book Website
John Wiley and Sons' Book Website
Optional (but highly recommended):
Verilog for Digital Design, Frank Vahid, Roman Lysecky, John Wiley and Sons
Note: Although "Verilog for Digital Design" is optional, a good Verilog HDL textbook is required for the course.
Grading for the class will be performed on an individual basis. You will not
be competing with the other students for your grade. If all students do well
in the class, it is possible everyone will get an A. Your grade is only
dependent on the effort you put into the class.
Letter grades will be assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B, 70% and above to a C, 60% and above to a D, and less than 60% to an E.
The grading will be based on a weighted sum as follows:
Punctuality: Please arrive on-time to class.
Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.
Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.
Regrades: All requests for regrades must be submitted in writing within one week of the distribution of graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem.
Cell Phones: Please turn your cell phone off before you come to class.
Late Homework: Late homework assignments will be accepted no later than the lecture immediately following the due date and will result in a 20% deduction in total possible points for the assignment.
May 08, 2008 – Final Sample Problems Solutions: As promised, solutions for the sample final problems have been posted in the glass case opposite my office (ECE 356F).
May 07, 2008 – Homework 5 Graded: Homework 5 has been graded and can be picked up outside of my office, ECE 356F. Solutions for Homework 5 have also been posted in the glass case opposite my office.
May 06, 2008 – Final Review: An optional review for the Final will be held Monday, May 12 from 5:00PM-7:00PM in ECE 530
May 05, 2008 – Final Sample Problems: Final Sample Problems have been posted. Note: The sample problems are representative of problems you can expected to see on the final. However, they are NOT an indication of the precise subset of material you will need to study for the final.
April 30, 2008 – Homework 5 Extension: Homework 5 is now due Monday, May 05 by 1:00PM.
April 25, 2008 – Lab 5 Extension: Lab 5 has been extended by one week for all lab sections. However, your Verilog code and Lab Report must still be submitted via D2L by May 02, 11:59PM.
April 07, 2008 – Homework 5: Homework 5 has been posted and is due Friday, May 02 at the beginning of lecture.
April 11, 2008 – Midterm 2 - The Sequel: An optional retest for Midterm 2 will held on Wednesday, April 16 during lecture. The retest will consist of a small subset of problems from the original Midterm fow which your score will be added to your original Midterm 2 score, but not to exceed a total score of 100 (unless extra credit points were awarded on the original Midterm assignment).
April 11, 2008 – Quiz 3: Quiz 3 has been rescheduled for Friday, April 25.
April 10, 2008 – HLSM Verilog Example: The Verilog code for the high-level state machine designed in lecture have been posted. Please note that this description uses a one procedure model. HLSMEx.v, HLSMExTB.v.
April 07, 2008 – Homework 4: Homework 4 has been posted and is due Friday, April 18 at the beginning of lecture.
March 31, 2008 – Midterm 2 Review: An optional review for Midterm 2 will be held Thursday, April 03 from 5:30PM-7:00PM in ECE 530
March 31, 2008 – Extra Credit Lab: An extra credit lab assingment has been posted. Details are provided below.
February 27, 2008 – Verilog Review/Debugging Seminars: Two optional Veriog Review/Debugging Seminars will held Friday, February 19 5:00-6:00PM and Monday, March 3 5:30-6:30PM in ECE 250. The seminar will consist of a breif review of Verilog design for combinational and sequential circuit and a guided debugging session. Within the guided debugging session, the students will need the following Verilog files. ExFSM.v, ExFSMTB.v.
February 27, 2008 – Midterm 1 - The Sequel: For Midterm 1, students may select a problem for which they did not receive full credit and submit a revised answer by Monday, March 3 (beginning of lecture, 12:05pm). The revised answer should be stabled as a separate page on top of the student's graded Midterm 1. Students will receive 50% credit for the resubmitted problem up to a maximum equal to the number of points the student missed for the selected problem. In other words, this is not an opportunity for extra credit.
February 26, 2008 – Quiz 2: Quiz 2 has been rescheduled for Wednesday, March 12.
February 26, 2008 – Homework 3: Homework 3 has been posted and is due Friday, March 14 at the beginning of lecture.
February 26, 2008 – Late Homework Policy Update: The policy for late homeworks has been revised. With updated policy, late homework assignments will be accepted no later than the lecture immediately following the due date and will result in a 20% deduction in total possible points for the assignment. This policy will be applied retroactively. If this affects your grade, please consult the instructor as soon as possible.
February 12, 2008 – Homework 2: Homework 2 has been posted and is due Monday, February 25 at the beginning of lecture. However, the homework problems are an excellent study aid for the midterm, and you may not want to wait until Monday to complete the assignment.
February 04, 2008 – Lecture 4 Design Challenge: The Design Challenge from Lecture 4 will be considered as part of the Design Challenge requirements, not as extra credit for homework as incorrectly noted in lecture notes. Lecture 4 has been updated accordingly.
January 24, 2008 – Homework 1: Homework 1 has been posted and is due Wednesday, February 06 at the beginning of lecture. Homework assignments received after 12:05 will be considered late.
January 18, 2008 – Lab Section 4 Cancelled : Section 4 (W 2:00PM-4:50PM) has been officially cancelled. All students previously enrolled in Section 4 have been moved to another section. If you need to change lab sections, please contact the instructor immediately.
SUBJECT TO CHANGE
|W||Jan 16:||Course Overview, Introduction to Digital Logic Design, Lecture 1 PDF|
|F||Jan 18:||Introduction to Digital Logic Design Lecture 1 PDF|
|M||Jan 21:||No Class (Martin Luther King, Jr. Day)|
|W||Jan 23:||Basic Logic Gates Lecture 2 PDF|
|F||Jan 25:||Combinational Logic, Boolean Algebra Lecture 3 PDF|
|M||Jan 28:||Combinational Logic Design Process, Lecture 4 PDF|
|W||Jan 30:||Combinational Logic Design Process, Common Combinational Components, Lecture 4 PDF|
|F||Feb 01:||Common Combinational Components, Lecture 4 PDF|
|M||Feb 04:||Quiz 1, Verilog: Combinational Logic Design, Verilog Lecture 1 PDF|
|W||Feb 06:||Verilog: Combinational Logic Design (cont.), Introduction to Sequential Logic, Basic Storage Element, Basic Register Design, Lecture 5 PDF|
|F||Feb 08:||Basic Storage Element, Basic Register Design (cont.), Controllers, Lecture 6 PDF|
|M||Feb 11:||Controllers (cont.), Lecture 6 PDF|
|W||Feb 13:||Sequential Logic Design Process, Lecture 7 PDF|
|F||Feb 15:||Sequential Logic Design Process (cont.), Lecture 7 PDF|
|M||Feb 18:||Review for Midterm|
|W||Feb 20:||No Class, Extended Office Hours - 12:00PM-2:00PM|
|F||Feb 22:||Midterm 1|
|M||Feb 25:||HDL (Verilog): Sequential Logic Design, Verilog Lecture 2 PDF|
|W||Feb 27:||Parallel Load, Shift, and Multifunction Registers, Lecture 8 PDF|
|F||Feb 29:||Adders: Half-Adder, Full-Adder, Carry-Ripple Adder, Lecture 9 PDF|
|M||Mar 03:||Shifters, Comparators, Incrementers, Lecture 10 PDF|
|W||Mar 05:||Shifters, Comparators, (cont.), Lecture 10 PDF|
|F||Mar 07:||Incrementers, Counters, Multipliers, Lecture 10 PDF|
|M||Mar 10:||Subtractors, Two's Complement, Overflow Lecture 11 PDF|
|W||Mar 12:||Quiz 2, ALUs, Register Files, Lecture 12 PDF|
|F||Mar 14:||HDL (Verilog): Datapath Components, Verilog Lecture 3 PDF|
|M||Mar 17:||No Class (Spring Break)|
|W||Mar 19:||No Class (Spring Break)|
|F||Mar 21:||No Class (Spring Break)|
|M||Mar 24:||HDL (Verilog): Datapath Components, Verilog Lecture 3 PDF|
|W||Mar 26:||Introduction to Register-Transfer-Level (RTL) Design, Lecture 13 PDF|
|F||Mar 28:||Introduction to Register-Transfer-Level (RTL) Design, Lecture 13 PDF|
|M||Mar 31:||Review for Midterm|
|W||Apr 02:||No Class, Office Hours - 12:00PM-1:00PM|
|F||Apr 04:||Midterm 2|
|M||Apr 07:||RTL Design Method and Examples, Lecture 14 PDF|
|W||Apr 09:||HDL (Verilog): RTL Design, Verilog Lecture 4 PDF|
|F||Apr 11:||RTL Design Method and Examples, Lecture 14 PDF|
|M||Apr 14:||Behavioral RTL Design: C to Gates, Lecture 15 PDF|
|W||Apr 16:||Midterm 2 (The Sequel), Memories: RAM/ROM/PROM, Lecture 16 PDF|
|F||Apr 18:||Memories: RAM/ROM/PROM, Lecture 16 PDF|
|M||Apr 21:||Optimization: Two-Level Minimization, Karnaugh Maps, Lecture 17 PDF|
|W||Apr 23:||Optimization: Exact and Heuristic Two-Level Minimization, Multi-Level Optimization, Lecture 17 PDF|
|F||Apr 25:||Quiz 3, Optimization: Exact and Heuristic Two-Level Minimization, Multi-Level Optimization, Lecture 17 PDF|
|M||Apr 28:||State Encodings, Mealy vs. Moore FSMs, Lecture 18 PDF|
|W||Apr 30:||Carry-Lookahead Adders, Lecture 19 PDF|
|F||May 02:||Implementation: Manufactured ICs, Field-Programmable Gate Arrays (FPGAs), Programmable Logic Devices (PLDs), Lecture 20 PDF|
|M||May 05:||Review for Final,|
|W||May 07:||No Class, Extended Office Hours - 12:00PM-2:00PM|
|W||May 14:||Final 11:00AM-1:00PM|
Homework 1 – Due Wednesday, February 06 (beginning of lecture by 12:05)
Digital Design: 1.7, 1.11, 1.22, 2.12, 2.17, 2.27, 2.38, 2.54, 2.59, 2.62, 2.71, 2.72, Extra Credit (5 points) 2.52
Homework 2 – Due Monday, February 25 (beginning of lecture by 12:05)
Digital Design: 3.6, 3.10, 3.16, 3.17, 3.28, 3.32, 3.29, 3.30, 3.38, 3.46, Extra Credit (5 points) 3.36
Homework 3 – Due Friday, March 14 (beginning of lecture by 12:05)
Digital Design: 4.3, 4.7, 4.9, 4.16, 4.25, 4.38, 4.45, 4.46, 4.53, 4.60, Extra Credit (5 points) 4.15
Homework 4 – Due Friday, April 18 (beginning of lecture by 12:05)
Digital Design: 5.4, 5.11, 5.12, 5.16, 5.23, Extra Credit (5 points) 5.26
Homework 5 – Due Monday, May 05 (1:00PM)
Digital Design: 6.2, 6.3, 6.10, 6.13, 6.24, 6.27, Extra Credit (5 points) 7.24
Labs must be finished on-time. Late labs will not be accepted. No extensions will be made for lab assignments.
Students should work in groups of two for laboratory assignments. However, students have the option of working on their own if computing resources permit. You must choose your lab partner during the first lab period and inform your TA of your selection. You lab partner will remain the same for the during of the semester. Please choose your lab partner wisely.
A lab report is required for all lab assignments (except Lab 1), using the provided template, ECE 274 Lab Report Template, and must be submitted via D2L as a Word or PDF file. Lab reports are due by 11:59 PM on the Friday of the week following the last scheduled lab session for each lab assignment. Individual labs may also require additional information such as schematics, simulations, manually performed tasks, or a summary of results. Please be sure to include this information in your lab report. Only one lab report is required for each group. Your lab report will count for 20% of each lab score.
|Lab 1 (Starts Jan 28 - Feb 01)
Duration: 1 Lab Session
|Introduction to Simulation and Synthesis||50|
|Lab 2 (Starts Feb 04 - Feb 08)
Duration: 2 Lab Sessions
|Binary to 7-segment Decoder||100|
|Lab 3 (Starts Feb 25 - Feb 29)
Duration: 2 Lab Sessions
|FSM for 4-bit Up/Down Counter||100|
|Lab 4 (Starts Mar 24 - Mar 28)
Duration: 2 Lab Sessions
|Binary to BCD Converter and Multiplexed BCD Display Driver||100|
|Lab 5 (Starts Apr 07 - Apr 11)
Duration: 3 Lab Sessions
|Extra Credit Lab