/*
 * Design: ECE 274 - Debounce Tester Display Circuit
 * Author: Roman Lysecky 
 * Copyright 2007, All Rights Reserved
 *
 * Date: Oct 11, 2007
 *
 * Note: Interfaces between DebounceTester circuit and LCD interface
 *       for displaying is test passed or failed.
 *
 */
 
`timescale 1ns / 1ns
module TesterDisplay(Clk, Rst, Fail, LCDOk, LCDFail, LCDUpdate, LCDAck);

   input Clk, Rst;
   input Fail;
   input LCDAck;
   output reg LCDOk, LCDFail;
   output reg LCDUpdate;
 
   parameter S_Init        = 0, 
             S_InitMsg     = 1,
             S_OkMsg       = 2,
             S_WaitForFail = 3,
             S_FailMsg     = 4,
             S_Failed      = 5;
             
   reg [2:0] State;
   reg [9:0] DelayTime;
   
   always @(posedge Clk) begin
      if (Rst == 1) begin
         State <= S_Init;
         LCDOk <= 0;
         LCDFail <= 0;
         LCDUpdate <= 0;
         DelayTime <= 0;
      end
      else begin
         // Default Values
         LCDOk <= 0;
         LCDFail <= 0;
         LCDUpdate <= 0;

         case (State) 
            S_Init: begin
               DelayTime <= 0;
               State <= S_InitMsg;
            end
   
            S_InitMsg: begin
               DelayTime <= DelayTime + 1;
               if( DelayTime >= 999 && Fail == 1) State <= S_FailMsg;
               else if( DelayTime >= 999 && Fail == 0) State <= S_OkMsg;
               else State <= S_InitMsg;
            end

            S_OkMsg: begin
               LCDOk <= 1;
               LCDUpdate <= 1;
               if (LCDAck == 1) State <= S_WaitForFail;
               else State <= S_OkMsg;
            end
            
            S_WaitForFail: begin
               if (Fail == 1) State <= S_FailMsg;
               else State <= S_WaitForFail;
            end
            
            S_FailMsg: begin
               LCDFail <= 1;
               LCDUpdate <= 1;
               if (LCDAck == 1) State <= S_Failed;
               else State <= S_FailMsg;
            end
            
            S_Failed: begin
               State <= S_Failed;
            end

            default: begin
               State <= S_Init;
               DelayTime <= 0;
            end
         endcase
      end
   end   
endmodule