/*
 * Design: ECE 274 - Top Level LCD Display Module  
 * Author: Roman Lysecky 
 * Copyright 2007, All Rights Reserved
 *
 * Date: Oct 11, 2007
 *
 */
 
`timescale 1ns / 1ns
module LCDDisplay(Clk, Rst, LCDOk, LCDFail, LCDUpdate, LCDAck, LCD_Data, LCD_E, LCD_RS, LCD_RW);

   input Clk, Rst;

   // ReactionTimer-LCD Interface
   input LCDOk, LCDFail;
   input LCDUpdate;
   output reg LCDAck;

   // LCD Interface
   output [11:8] LCD_Data;
   output LCD_E, LCD_RS, LCD_RW;
   
   parameter InitString =     "Debouncer Test  ";
   parameter PassString =     "Debouncer OK    ";
   parameter FailString =     "Debouncer Fail  ";

   parameter S_Init = 0, 
             S_Wait = 1, 
             S_LCDAck = 2,
             S_Pass = 3,
             S_Fail = 4;
   
   reg [8*16:1] Display;
   reg [3:0] State;
   reg GO;
   
   LCDInterface LCDInterface_0 (Clk, Rst, GO, Display, LCD_Data, LCD_E, LCD_RS, LCD_RW);
   
   always @(posedge Clk) begin
      if( Rst == 1 ) begin
         State <= S_Init;
         LCDAck <= 0;
         GO <= 0;
         Display <= InitString;
      end
      else begin
         LCDAck <= 0;
         case( State )
            S_Init: begin
               Display <= InitString;
               GO <= 1;
               State <= S_Wait;
            end

            S_Wait: begin
               GO <= 0;
               if (LCDOk == 1 && LCDUpdate == 1) begin
                  State <= S_Pass;
               end
               else if (LCDFail == 1 && LCDUpdate == 1) begin
                  State <= S_Fail;
               end
               else begin
                  State <= S_Wait;
               end
            end
            
            S_Pass: begin
               GO <= 1;
               Display <= PassString;
               State <= S_LCDAck;
            end

            S_Fail: begin
               GO <= 1;
               Display <= FailString;
               State <= S_LCDAck;
            end

            S_LCDAck: begin
               LCDAck <= 1;
               if (LCDUpdate == 1) begin
                  State <= S_LCDAck;
               end
               else begin
                  State <= S_Wait;
               end
            end

         endcase
      end
   end
endmodule