/*
 * Design: 50 MHz -> 20 kHz Clock Divder
 * Author: Roman Lysecky 
 * Copyright 2008, All Rights Reserved
 *
 * Date: March 25, 2007
 *
 */
 
`timescale 1ns / 1ns
module ClkDiv20kHz(Clk, Rst, ClkOut);

   input Clk, Rst;
   output reg ClkOut;
  
   parameter DivVal = 1250;
   reg[24:0] DivCnt;
   reg ClkInt;
   
   always @(posedge Clk) begin
      if( Rst == 1 )begin
         DivCnt <= 0;
         ClkOut <= 0;
         ClkInt <= 0;
      end
      else begin
         if( DivCnt == (DivVal-1) ) begin
            ClkOut <= ~ClkInt;
            ClkInt <= ~ClkInt;
            DivCnt <= 0;
         end
         else begin
            ClkOut <= ClkInt;
            ClkInt <= ClkInt;
            DivCnt <= DivCnt + 1;
         end
      end
   end
endmodule