/*
 * Design: ECE 274 - Top Level Design Module for Reaction Timer 
 * Author: Roman Lysecky 
 * Copyright 2007, All Rights Reserved
 *
 * Date: August 19, 2008
 *
 */

`timescale 1ns / 1ns
module Top(Clk, Rst, DivRst, Start, LED, LCD_Data, LCD_E, LCD_RS, LCD_RW); 

   input Clk, Rst, DivRst;
   input Start;
   output [7:0] LED;
   output [11:8] LCD_Data;
   output LCD_E, LCD_RS, LCD_RW;

   wire ClkMS, ClkLCD;
   wire [ ] RandomValue;  // You need to determine the # of bits
   wire [9:0] ReactionTime;
   wire Cheat, Slow, Wait, LCDUpdate, LCDAck;
   
   ClkDiv ClkDiv_0 (Clk, DivRst, ClkMS);
   LCDClkDiv LCDClkDiv_0 (Clk, DivRst, ClkLCD);
   ReactionTimer ReactionTimer_0 (ClkMS, Rst, Start, LED, ReactionTime, Cheat, Slow, Wait, RandomValue, LCDUpdate, LCDAck);
   RandomGen RandomGen_0 (ClkMS, Rst, RandomValue);
   LCDDisplay LCDDisplay_0 (ClkLCD, Rst, Cheat, Slow, Wait, ReactionTime, LCDUpdate, LCDAck, LCD_Data, LCD_E, LCD_RS, LCD_RW);

endmodule