Lab 1

Lab 1: Introduction to Verilog Simulation and Synthesis

Starts: Week 3 (Sep 08-Sep 12)
Demo Due: Week 3 (Sep 08-Sep 12)
Code Due: Friday, Sep 12, 11:59PM
Points: 50

Pre-Lab Assignment

None.

Files

• Xilinx ISE Simulation Tutorial
• Xilinx ISE Synthesis Tutorial

Lab Overview:

In this lab, you will design a library of basic logic gates including a 2-input AND gate, a 2-input OR gate, and an inverter (INV gate). Using these basic components, one can build any combinational logic circuit.

Lab Procedure and Demo:

1. 2-input AND gate (30 points)
   • Follow the Verilog simulation tutorial to design a 2-input AND gate. Test your design exhaustively simulating all possible combinations. (15 points)
   • Follow the Verilog synthesis tutorial to download your 2-input AND gate design to the Spartan-3E Starter board. Test your design exhaustively trying all possible combinations. (15 points)
2. 2-input OR gate (15 points)
   • Design a 2-input OR gate. Test your design exhaustively simulating all possible combinations.
   • Download your 2-input OR gate onto the Spartan-3E Starter board. Test your design exhaustively trying all possible input combinations.
3. INV gate (5 points)
   • Design an inverter (INV gate). Test your design exhaustively simulating all possible combinations.

Lab Report/Code Requirements

No lab report is required for the first lab.