Roman Lysecky (firstname.lastname@example.org)
Office Hours: MW 1:00-2:00PM, F 2:00-3:00PM, or by appointment.
Office: ECE 356F
MWF 12:00-12:50PM, ILC 150
|Section 1:||M 2:00PM-4:50PM,||ECE 301,||TA: Haiyong Zhang|
|Section 3:||T 2:00PM-4:50PM,||ECE 301,||TA: Haiyong Zhang|
|Section 5:||T 11:00AM-1:50PM,||ECE 301,||TA: Haiyong Zhang|
|Section 6:||R 11:00AM-1:50PM,||ECE 301,||TA: Lance Saldanha|
|Section 7:||R 2:00PM-4:50PM,||ECE 301,||TA: Lance Saldanha|
Haiyong Zhang, (email@example.com)
Lance Saldanha, (firstname.lastname@example.org)
Digital Design, Frank Vahid, John Wiley and Sons
Frank Vahid's Book Website
John Wiley and Sons' Book Website
Optional (but recommended):
Verilog for Digital Design, Frank Vahid, Roman Lysecky, John Wiley and Sons
Grading for the class will be performed on an individual basis. You will not
be competing with the other students for your grade. If all students do well
in the class, it is possible everyone will get an A. Your grade is only
dependent on the effort you put into the class. Letter grades will be
assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B,
70% and above to a C, 60% and above to a D, and less than 60% to an E.
The grading will be based on a weighted sum as follows:
Punctuality: Please arrive on-time to class.
Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.
Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.
Regrades: All requests for regrades must be submitted in writing within one week of the distribution of graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem.
Cell Phones: Please turn your cell phone off before you come to class.
Late Homework: Late homework assignments will be accepted for a maximum of two days after the due date. For each day your assignment is late, 20% of the total possible points will be deducted from your score.
November 19, 2007 – Lab 5 Report Due Date: Lab 5 reports will be due Wednesday, December 5 before 11:59PM for all lab sections. You can turn in your Lab 5 report in my mailbox, slide it under my office door, send me an Word or PDF file via email, or coordinate directly with your TA.
November 19, 2007 – Lab 5 Due Date: The following provides the due dates for Lab 5. As all course work must be completed by Wednesday, December 5, no further extensions can be provided.
|Section 1:||M 2:00PM-4:50PM,||Monday, December 3, 3:00PM|
|Section 3:||T 2:00PM-4:50PM,||Tuesday, November 27, End of lab,|
|Section 5:||T 11:00AM-1:50PM,||Tuesday, November 27, End of lab,|
|Section 6:||R 11:00AM-1:50PM,||Thursday, November 29, End of lab,|
|Section 7:||R 2:00PM-4:50PM,||TBD - Due to a power outage on November 15, please consult your TA to determine your lab due date,|
November 15, 2007 – Review of Midterm 2: The review of Midterm 2 will be held on Monday, November 19 and Tuesday, November 20 at 5:00 PM in room ECE 530.
November 12, 2007 – Homework 5: Homework 5 has been posted and is due Monday, Dec 03 at the beginning of lecture. Homework assignments received after 12:05 will be considered late.
October 29, 2007 – Quiz 3: Quiz 3 is scheduled for Monday, November 19, 2007.
October 23, 2007 – Lab 4 Extension: Lab 4 has been extended by one week. Although an extension has been given, this should not imply that you can wait another week to work on Lab 4. Lab 4 requires some non-trivial design effort which is best completed before attending your designated lab section.
October 16, 2007 – Lab 4 Clarification: While logic gates may be used within your Lab 4 assignment, they should only be used when absolutely necessary. The Binary to BCD Converter and Refresher components must be designed using the approved datapath components, where each datapath component is implemented as a behavioral Verilog description.
October 15, 2007 – Lab 4 Report: Your Lab 4 Report should include a schematic diagram for the Binary to BCD Converter, Multiplexed BCD Display Driver, and Refresher components clearly indicating the various datapath components utilized and their interconnections.
October 12, 2007 – Lab 5: Lab 5 has been posted.
October 05, 2007 – Homework 3: Homework 3 has been posted and is due Wednesday, October 17 at the beginning of lecture. Homework assignments received after 12:05 will be considered late.
October 05, 2007 – Lab 4 & 5 Code Submission Requirement: For Lab 4 & 5, each group must submit all of their structural and behavioral Verilog code to the appropriate dropbox on the D2L course website by deadline specified within each lab description. Your online code submission will count for 5 points of your lab report score for those labs. Only one submission is required per group, but you must identify yourself and your lab partner within comments at the top of all your Verilog files.
October 03, 2007 – Lab 4: Lab 4 has been posted.
October 03, 2007 – Lab 3 Extension: Lab 3 has been extended by 30 minutes. Although no official labs have been scheduled for next week, the TA's will be present to provide a 30 minute extension to Lab 3 and to provide the opportunity for students to work ahead on Lab 4 (which should be posted later today). Lab 4 will begin for all lab section the week of Oct. 15.
September 28, 2007 – Solutions Posted: Solutions for Homework Assignments 1 & 2, and Quiz 1 have been posted in the glass case opposite my office (ECE 356F). Sample midterm problems (some of which are previous midterms) have also been posted. Solutions for the sample midterm problems will not be provided.
September 17, 2007 – Quiz 1.1: An optional 5-minute 2 point quiz will be held this Friday, September 21 at the beginning of lecture. Quiz 1.1 will be counted towards your Quiz 1 grade and will be very similar to Quiz 1. Please be prepared!
September 16, 2007 – Homework 2: Homework 2 has been posted and is due Wednesday, September 26 at the beginning of lecture. Homework assignments received after 12:05 will be considered late.
August 29, 2007 – Homework 1: Homework 1 has been posted and is due Monday, September 10 at the beginning of lecture. Homework assignments received after 12:05 will be considered late.
August 27, 2007 – Lab: Lab start this week. Be sure to attend your lab section.
August 27, 2007 – Lecture 2, Slide 12: Slide 12 of Lecture 2 continues to be plagued with problems. An updated version of Lecture 2 slides has been posted with additional examples describing converting English to Boolean equations. The revisions will be further discussed in lecture on Wednesday, August 29th.
August 24, 2007 – Lecture Slides: Please note that lecture slides may be updated shortly before or after lecture on the day of lecture. For instance, lectures 2 and 3 were updated today immediately before lecture.
August 20, 2007 – Textbooks: The UA Bookstore has the incorrect textbook (VHDL for Digital Design) for ECE 274. The correct textbook is Digital Design and may still be found in the UA bookstore. The optional textbook for the course is Verilog for Digital Design. The bookstore has been made aware of this problem and should be ordering the correct books shortly. The Verilog book will be used heavily starting with your second lab assignment. Although Verilog is used in your first lab assignment, your TAs will be able to provide the required Verilog knowledge needed.
SUBJECT TO CHANGE
|M||Aug 20:||Course Overview, Introduction to Digital Logic Design, Lecture 1 PDF|
|W||Aug 22:||Introduction to Digital Logic Design, Basic Logic Gates, Lecture 2 PDF|
|F||Aug 24:||Combinational Logic, Boolean Algebra, Lecture 3 PDF|
|M||Aug 27:||Combinational Logic, Boolean Algebra (cont.), Lecture 3 PDF|
|W||Aug 29:||Combinational Logic Design Process, Lecture 4 PDF|
|F||Aug 31:||Combinational Logic Design Process (cont.), Common Combinational Components, Lecture 4 PDF|
|M||Sep 03:||No Class (Labor Day)|
|W||Sep 05:||Hardware Description Languages (HDL): Introduction to Verilog and Combinational Logic Design, Verilog Lecture 1 PDF|
|F||Sep 07:||Introduction to Sequential Logic, Basic Storage Element, Lecture 5 PDF|
|M||Sep 10:||Basic Register Design, Controllers, Lecture 6 PDF|
|W||Sep 12:||Sequential Logic Design Process, Lecture 7 PDF|
|F||Sep 14:||Quiz 1, Sequential Logic Design Process, Lecture 7 PDF|
|M||Sep 17:||Sequential Logic Design Process: Common Pitfalls and Additional Considerations, Lecture 8 PDF|
|W||Sep 19:||HDL (Verilog): Sequential Logic Design, Verilog Lecture 2 PDF|
|F||Sep 21:||Quiz 1.1, Parallel Load, Shift, and Multifunction Registers, Lecture 9 PDF|
|M||Sep 24:||Adders: Half-Adder, Full-Adder, Lecture 10 PDF|
|W||Sep 26:||Adders: Carry-Ripple Adder, Lecture 10 PDF|
|F||Sep 28:||Review for Midterm|
|M||Oct 01:||No Class, Extended Office Hours - 12:00PM-2:00PM|
|W||Oct 03:||Midterm 1|
|F||Oct 05:||Shifters, Comparators, Incrementers, Lecture 11 PDF|
|M||Oct 08:||Counters, Multipliers, Lecture 11 PDF|
|W||Oct 10:||Subtractors, Two's Complement, Overflow Lecture 12 PDF|
|F||Oct 12:||ALUs, Register Files, Lecture 13 PDF|
|M||Oct 15:||HDL (Verilog): Datapath Components, Verilog Lecture 3 PDF|
|W||Oct 17:||Introduction to Register-Transfer-Level (RTL) Design, Lecture 14 PDF|
|F||Oct 19:||RTL Design Method, Lecture 14 PDF|
|M||Oct 22:||Quiz 2, RTL Design Method, RTL Design Examples, Lecture 15 PDF|
|W||Oct 24:||RTL Design, Lecture 15 PDF|
|F||Oct 26:||RTL Design, Lecture 15 PDF|
|M||Oct 29:||Behavioral RTL Design: C to Gates, Lecture 16 PDF|
|W||Oct 31:||HDL (Verilog): RTL Design, Verilog Lecture 4 PDF|
|F||Nov 02:||Review for Midterm|
|M||Nov 05:||No Class, Extended Office Hours - 12:00PM-2:00PM|
|W||Nov 07:||Midterm 2|
|F||Nov 09:||Memories: RAM/ROM/PROM, Lecture 17 PDF|
|M||Nov 12:||No Class (Veterans Day)|
|W||Nov 14:||Optimization: Two-Level Minimization, Karnaugh Maps, Lecture 18 PDF|
|F||Nov 16:||Optimization: Exact and Heuristic Two-Level Minimization, Multi-Level Optimization, Lecture 18 PDF|
|M||Nov 19:||Quiz 3, State Encondings, Mealy vs. Moore FSMs, Lecture 19 PDF|
|W||Nov 21:||No Class|
|F||Nov 23:||No Class (Thanksgiving Break)|
|M||Nov 26:||Carry-Lookahead Adders, Lecture 20 PDF|
|W||Nov 28:||Implementation: Manufactured ICs, Lecture 21 PDF|
|F||Nov 30:||Implementation: Field-Programmable Gate Arrays (FPGAs), Programmable Logic Devices (PLDs), Lecture 21 PDF|
|M||Dec 03:||Review for Final,|
|W||Dec 05:||No Class, Extended Office Hours - 12:00PM-2:00PM|
|F||Dec 14:||Final 11:00AM-1:00PM|
Homework 1 – Due Monday, September 10 (beginning of lecture by 12:05)
Digital Design: 1.6, 1.8, 1.9, 1.17, 1.23, 2.11, 2.16, 2.22, 2.26, 2.36, 2.37, 2.48, 2.55, 2.69, 2.79
Homework 2 – Due Wednesday, September 26 (beginning of lecture by 12:05)
Digital Design: 3.4, 3.6, 3.13, 3.25, 3.29, 3.30, 3.32, 3.39, 3.42, 3.45, Extra Credit (5 points) 3.51
Homework 3 – Due Wednesday, October 17 (beginning of lecture by 12:05)
Digital Design: 4.3, 4.9, 4.10, 4.19, 4.22, 4.27, 4.29, 4.38, 4.47, 4.50, 4.54, 4.59, Extra Credit (5 points) 4.55
Homework 4 – Due Wednesday, November 14 (beginning of lecture by 12:05)
Digital Design: 5.1, 5.3, 5.6, 5.12, 5.17, 5.23, 5.24, 5.25, 5.32, 5.35, Extra Credit (10 points) 5.9
Homework 5 – Due Monday, Dec 03 (beginning of lecture by 12:05)
Digital Design: 6.2, 6.6, 6.7, 6.10, 6.14, 6.19, 6.22, 6.24, 6.27, 6.30, Extra Credit (10 points) 6.35
Quiz 1 – September 14
Quiz 2 – October 22
Quiz 3 – November 19
Labs must be finished on-time. Late labs will not be accepted. A lab report, using the specified lab report format, is required for all lab assignments, including tutorials, and is due at the beginning of the following lab period after the lab is due. Individual labs may also require additional information such as schematics, simulations, manually performed tasks, or a summary of results. Please be sure to include this information in your lab report. Your lab report will count for 20% of each lab score.
Students should work in groups of two for laboratory assignments. However, students have the option of working on their own if computing resources permit. You must choose your lab partner during the first lab period and inform your TA of your selection. You lab partner will remain the same for the during of the semester. Please choose your lab partner wisely.
|Lab 1 (Starts Aug 27 - Aug 31)
Duration: 2 Lab Sessions
|Introduction to Simulation and Synthesis||50|
|Lab 2 (Starts Sep 10 - Sep 14)
Duration: 2 Lab Sessions
|Binary to 7-segment Decoder||100|
|Lab 3 (Starts Sep 24 - Sep 28)
Duration: 2 Lab Sessions
|FSM for 4-bit Up/Down Counter||100|
|Lab 4 (Starts Oct 15 - Oct 19)
Duration: 2 Lab Sessions
|Binary to BCD Converter and Multiplexed BCD Display Driver||100|
|Lab 5 (Starts Nov 05 - Nov 09)
Duration: 3 Lab Sessions