Lab 4 - Datapath Component Design - Adder and Comparator Design
In this lab, you will learn how to behaviorally and structurally design a
4-bit adder and behaviorally design a 4-bit less-than comparator.
Lab Procedure
The following provides the steps that you must follow to complete this lab.
- Behaviorally design a full-adder.
- Using your for full-adder design, structural create a 4-bit carry-ripple adder with carry out, co.
- Test your 4-bit adder design. It is a good strategy to tests the boundary cases of a digital circuit. For example, for your
4-bit adder design, you should test the addition of 1111+1111 and 0000+0000. You might also want to test 1111+0001 to test the
carry-ripple logic. In addition, you should test a few cases with various values in the middle of the inputs range.
- Behaviorally design the same 4-bit adder using the "+" operators to add
the two four bit inputs. In your behaviorally design, you do not need to worry
about the carry output.
- Test your behavioral 4-bit adder design using the same strategy as above.
- Extra Credit: Modify your behavioral 4-bit adder design
to include a carry out, co, using only a few extra lines of Verilog code.
You may to lookup the difference between blocking and non-blocking statements
in Verilog.
- Behaviorally design a 4-bit less-than comparator. The comparator should have two 4-bit
inputs, a and b, and a single output, lt. lt should
output 1 if a < b and 0 otherwise.
- Test your behavioral less-than comparator design using a similar strategy as you did for the 4-bit adder.
Demo
You must demo the following aspects or your designs to the TA.
- Verilog code for full-adder and structural 4-bit adder design.
- Simulation waveforms demonstrating correct functionality for your structural 4-bit adder design.
- Verilog code for behavioral 4-bit adder design.
- Simulation waveforms demonstrating correct functionality for your behavioral 4-bit adder design.
- Verilog code for behavioral less-than comparator design.
- Simulation waveforms demonstrating correct functionality for your less-than comparator design.
Lab Report
In addition to the standard lab report format, you must submit the following information.
- Verilog code for behavioral and structural 4-bit adder design.
- Simulation waveforms demonstrating correct functionality for the structural and behavioral
adder design.
- Verilog code for behavioral 4-bit less-than comparator design.
- Simulation waveforms demonstrating correct functionality for the comparator design.
- Provide a description of testing strategy for the 4-bit less-than comparator. Be sure
to specify how you tested the boundary cases.