Lab 3 - NAND Gate Design

In this lab, you will design a 2-input NAND gate using the same techniques learned in the previous lab/tutorial. In designing the layout of your NAND, you should strive to create a design that is as compact as possible while still adhering to the design rules.

Lab Procedure

The following provides the steps that you must follow to complete this lab.

1. Design and test transistor schematic for NAND gate.
2. Design and test layout for NAND gate

Demo

You must demo the following aspects or your NAND gate design to the TA.

1. NAND gate schematic design and simulation.
2. NAND gate layout design and extracted layout simulation.

Lab Report

In addition to the standard lab report format, you must submit the following information.

1. NAND gate schematic.
2. NAND gate layout.
3. NAND gate extracted layout simulation.