.: Core Research Activities in
Reconfigurable Computing Laboratory
Please refer to Reconfigurable Architecture for Neuromoprhic Computing (RANC) project page for current state of the project.
Funded by: Raytheon
Collaborator: Air Force Research Labs
Students: JoshuaMack, Nirmal Kumbhare, Edward Richter, Ruben Purdy, Spencer Valancius, John Mixter
Applications and Architectures of Neuromorphic Computing
In this project we are building an open source C++ software simulation and Field Programmable Gate Array (FPGA) emulation environment of the TrueNorth architecture. These technologies will provide a flexible hardware framework for neuromorphic architectural research to:
- further understand the TrueNorth architecture design decisions
- make TrueNorth architecture accessible for researchers and application developers through a programming and testing environment
- enable researchers to feasibly alter architectural features and investigate the relationship between network parameters (training methods, binary spikes, thresholds, leak values, synaptic weights) and performance metrics (classification accuracy and energy efficiency).
To the best of our knowledge there is no such flexible hardware platform publicly available to perform design space exploration on neuromorphic architectures for deep learning research. The source code for our software simulation is available here
Growing Neural Networks
The low size, weight and power (SWaP) requirements in embedded systems restrict the amount of memory and processing power available to execute a neural network. The state of the art neural networks tend to be quite large and fitting them into severely constrained hardware has proven to be difficult. In order to both train and execute inference in low SWaP embedded hardware a new method is needed. We are investigating ways to grow small yet accurate neural networks within embedded hardware.