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The MyHDL manual

Jan Decaluwe

Email: jan@jandecaluwe.com

Release 0.4
February 4, 2004

Copyright 2003 Jan Decaluwe. All rights reserved.

Abstract:

MyHDL is a Python package for using Python as a hardware description and verification language. Languages such Verilog and VHDL are compiled languages. Python with MyHDL can be viewed as a "scripting language" counterpart of such languages. However, Python is more accurately described as a very high level language (VHLL). MyHDL users have access to the amazing power and elegance of Python.

The key idea behind MyHDL is to use Python generators for modeling hardware concurrency. A generator is a resumable function with internal state. In MyHDL, a hardware module is modeled as a function that returns generators. With this approach, MyHDL directly supports features such as named port association, arrays of instances, and conditional instantiation.

MyHDL supports the classic hardware description concepts. It provides a signal class similar to the VHDL signal, a class for bit oriented operations, and support for enumeration types. The Python yield statement is used as a general sensitivity list to wait on a signal change, an edge, a delay, or on the completion of another generator. MyHDL supports waveform viewing by tracing signal changes in a VCD file.

Python's rare combination of power and clarity makes it ideal for high level modeling. It can be expected that MyHDL users will often have the ``Pythonic experience'' of finding an elegant solution to a complex modeling problem. Moreover, Python is outstanding for rapid application development and experimentation.

With MyHDL, the Python unit test framework can be used on hardware designs. MyHDL can also be used as hardware verification language for VHDL and Verilog designs, by co-simulation with any simulator that has a PLI. The distribution contains a PLI module for the Icarus Verilog simulator.

Finally, a subset of MyHDL code can be converted automatically to synthesizable Verilog code. This feature provides a direct path from Python to an FPGA or ASIC implementation.

The MyHDL software is open source software. It is licensed under the GNU Lesser General Public License (LGPL).


Sections marked with * have suggested edits by David MacQuigg. Search for ### in text.


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Release 0.4, documentation updated on February 4, 2004.

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