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2.2 Concurrent generators and signals

In the previous section, we simulated a single generator. Of course, real hardware descriptions are not like that: in fact, they are typically massively concurrent. MyHDL supports this by allowing an arbitrary number of concurrent generators.

With concurrency comes the problem of deterministic communication. Hardware languages use special objects to support deterministic communication between concurrent code. MyHDL has a Signal object which is roughly modeled after VHDL signals.

We will demonstrate these concepts by extending and modifying our first example. We introduce a clock signal, driven by a second generator:

from myhdl import delay, now, Simulation, Signal, posedge       ###1
clk = Signal(0)  # clk is a Signal with initial value 0         ###
 
def clkGen():
    while True:             ###2
        yield delay(10)
        clk.next = 1
        yield delay(10)
        clk.next = 0

The clk signal is constructed with an initial value 0. In the clock generator function clkGen, it is continuously assigned a new value after a certain delay. In MyHDL, the new value of a signal is specified by assigning to its next attribute. This is the MyHDL equivalent of the VHDL signal assignment and the Verilog non-blocking assignment.

The sayHello generator function is modified to wait for a rising edge of the clock instead of a delay:

def sayHello():
    while True:             ###2
        yield posedge(clk)
        print "%s Hello World!" % now()

Waiting for the clock edge is achieved with a second form of the yield statement: "yield posedge(signal)". At that point, the generator will wait for a rising edge on the signal. ###3

The Simulation is now constructed with 2 generator arguments:

sim = Simulation(clkGen(), sayHello())
sim.run(50)

When we run this simulation, we get:

% python hello2.py
10 Hello World!
30 Hello World!
50 Hello World!
StopSimulation: Simulated for duration 50

###1  Best to include any line that has changed from the previous example.  Students new to Python may not realize that the new objects are not some built-in feature of Python.

###2  See 2.1 notes.

###3  Waiting for the clock edge is achieved by returning a different object "posedge(signal)".  The simulator will use this object to schedule the next call to sayHello.

Again, students don't know what is standard Python, and what is MyHDL.  We want to avoid any implication that this is a different form of Python's yield statement.

 

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Release 0.4, documentation updated on February 4, 2004.

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