PROJECT
    1. Competition (due 05/04/10)
      • Projects passing all 3 phases are eligible
      • Synthesize your design
      • You must use MIPS ISA. No other instructions are allowed.
      • If you think there are better instructions in MIPS that were not required in phase 2 and if you want to use those for your algorithm, that is acceptable.
      • Collect synthesis report (critical path delay, clock rate, etc)
      • Demonstrate the functionality on the FPGA with the SAD assembly code
      • You may choose to run the algorithm you implemented or implement another version. Code optimizations are suggested.
      • Use the LCD of the FPGA board to display the corrdinates of the block with the minimum SAD. LCD display interface with the .ucf file for putting two integer values on the LCD is posted here
      • Projects will be ranked based on maximum operational frequency of the datapath. Top 7 groups will be eligible for bonus credits which will be directly added to overall class score.
    2. Bonus (due 05/04/10)
      • Projects passing all 3 phases are eligible for bonus
      • Design pipelined version of your datapth
      • Synthesize your design
      • Run it on FPGA board using your assembly code
      • Use the LCD of the FPGA board to display the coordinates of the block with the minimum SAD.
      • There is no partial credit.