PROJECT

Project Phase I Simple datapath: In Phase II we will modify this datapath based on the Instruciton Set Architecture. In Phase I we will design and test the componenets of the system in Verilog.

Demo Procedures:
o Make an appointment with the TA to demonstrate the functionality of your modules
o Show up during your designated time slot
o Simulate the behavior of each module using your own testbenches.

1) (25 points) Design a register file module that has the following format:
module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister,
WriteData, RegWrite, Clk, ReadData1, ReadData2);
input [4:0] ReadRegister1, ReadRegister2; // Two registers to be read
input [4:0] WriteRegister; // Register address to write into
input [31:0] WriteData; // Data to be written into WriteRegister
input RegWrite; // RegWrite control signal. Data is written
// only when this signal is enabled
Input Clk;
output [31:0] ReadData1, ReadData2;

ReadRegister1 and ReadRegister2 are two 5-bit addresses to read two registers simultaneously. The two 32-bit data sets are available on ports ReadData1 and ReadData2, respectively. ReadData1 and ReadData2 are registered outputs (output of register file is written into these registers at the falling edge of the clock). You can view it as if outputs of registers specified by ReadRegister1 and ReadRegister2 are written into output registers ReadData1 and ReadData2 at the falling edge of the clock. (Note: We will design register file (in real hardware) such that the contents of registers do not change for a pre-specified time before the falling edge of the clock arrives to allow for data multiplexing and setup time.)

RegWrite signal is high during the rising edge of the clock if the input data is to be written into the register file. The contents of register specified by address WriteRegister in the register file are modified at the rising edge of the clock if RegWrite signal is high. The D-flip flops in the register file are positive-edge (rising-edge) triggered. (You have to use this information to generate the write-clock properly.)

2) (25 points) Design a DataMemory module that has the following format:
module DataMemory(Address, WriteData, MemRead, MemWrite, Clk, ReadData);
input [31:0] Address; // 32-bit address to memory.
input [31:0] WriteData; // Data to be written into WriteRegister
input MemRead; // Data in memory location Address is read if
// this control is set
Input Clk;
Input MemWrite; // WriteData is written in Address during
// positive clock edge if this control is set
output [31:0] ReadData; // Value read from memory location Address

Design the above memory similar to the RegisterFile model. Design uses only 512 of 32-bit memory elements. For this purpose, assume that we will use only least significant 9 bits out of the 32-bit address computed by your ALU.

ReadData will have the value stored in the memory indexed by Address input if MemRead is 1, otherwise, it is 0x00000000. The reading of memory is not clocked.

3) (20 points) Design an Instruction Memory module that has the following format:
module InstructionMemory(Address, Clk, ReadData);
input [31:0] Address; // 32-bit address to memory.
input Clk;
output [31:0] ReadData; // Value read from memory location Address

Design the above memory similar to the DataMemory model. Design uses only256 of 32-bit memory elements. For this purpose, assume that we will use only least significant 8 bits out of the 32-bit PC register.

4) (30 points)
Design a 2-input 32-bit multiplexor, a 2-input 5-bit multiplexor and a sign extension unit. Modules must have the following format:

module Mux32Bit2To1(a, b, op, result);
// 2 to 1 mux : if op is 1 then choose "a", if op is 0 then choose "b"
input [31:0] a, b; // 32-bit inputs
input op; // one-bit selection input
output [31:0] result; // 32-bit output

module Mux5Bit2To1(a, b, op, result);
input [4:0] a, b; // 5-bit inputs
input op; // one-bit selection input
output [4:0] result; // 5-bit output

Design a 16 to 32-bit sign extension unit. (You can use "assign" statement)
module SignExtension(a, result);
// Sign extension is the operation, in computer arithmetic, of increasing the number of //bits of a binary number while preserving the number's sign (positive/negative). This is //done by appending digits to the most significant side of the number, following a //procedure dependent on the particular signed number representation used.
input [15:0] a; // 16-bit input
output [31:0] result; // 32-bit output